| 1 | /*
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| 2 | * Copyright (c) 2005 Jakub Jermar
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup sparc64interrupt
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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| 35 | #include <arch/interrupt.h>
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| 36 | #include <arch/sparc64.h>
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| 37 | #include <arch/trap/interrupt.h>
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| 38 | #include <interrupt.h>
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| 39 | #include <ddi/irq.h>
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| 40 | #include <arch/types.h>
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| 41 | #include <debug.h>
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| 42 | #include <arch/asm.h>
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| 43 | #include <arch/barrier.h>
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| 44 | #include <print.h>
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| 45 | #include <arch.h>
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| 46 | #include <mm/tlb.h>
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| 47 | #include <config.h>
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| 48 | #include <synch/spinlock.h>
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| 49 |
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| 50 | /** Register Interrupt Level Handler.
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| 51 | *
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| 52 | * @param n Interrupt Level (1 - 15).
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| 53 | * @param name Short descriptive string.
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| 54 | * @param f Handler.
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| 55 | */
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| 56 | void interrupt_register(int n, const char *name, iroutine f)
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| 57 | {
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| 58 | ASSERT(n >= IVT_FIRST && n <= IVT_ITEMS);
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| 59 |
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| 60 | exc_register(n - 1, name, f);
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| 61 | }
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| 62 |
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| 63 | /** Process hardware interrupt.
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| 64 | *
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| 65 | * @param n Ignored.
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| 66 | * @param istate Ignored.
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| 67 | */
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| 68 | void interrupt(int n, istate_t *istate)
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| 69 | {
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| 70 | uint64_t status;
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| 71 | uint64_t intrcv;
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| 72 | uint64_t data0;
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| 73 | status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
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| 74 | if (status & (!INTR_DISPATCH_STATUS_BUSY))
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| 75 | panic("Interrupt Dispatch Status busy bit not set.");
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| 76 |
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| 77 | intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0);
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| 78 | #if defined (US)
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| 79 | data0 = asi_u64_read(ASI_INTR_R, ASI_UDB_INTR_R_DATA_0);
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| 80 | #elif defined (US3)
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| 81 | data0 = asi_u64_read(ASI_INTR_R, VA_INTR_R_DATA_0);
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| 82 | #endif
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| 83 |
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| 84 | irq_t *irq = irq_dispatch_and_lock(data0);
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| 85 | if (irq) {
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| 86 | /*
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| 87 | * The IRQ handler was found.
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| 88 | */
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| 89 | irq->handler(irq);
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| 90 | /*
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| 91 | * See if there is a clear-interrupt-routine and call it.
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| 92 | */
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| 93 | if (irq->cir) {
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| 94 | irq->cir(irq->cir_arg, irq->inr);
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| 95 | }
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| 96 | spinlock_unlock(&irq->lock);
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| 97 | } else if (data0 > config.base) {
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| 98 | /*
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| 99 | * This is a cross-call.
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| 100 | * data0 contains address of the kernel function.
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| 101 | * We call the function only after we verify
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| 102 | * it is one of the supported ones.
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| 103 | */
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| 104 | #ifdef CONFIG_SMP
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| 105 | if (data0 == (uintptr_t) tlb_shootdown_ipi_recv) {
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| 106 | tlb_shootdown_ipi_recv();
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| 107 | }
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| 108 | #endif
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| 109 | } else {
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| 110 | /*
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| 111 | * Spurious interrupt.
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| 112 | */
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| 113 | #ifdef CONFIG_DEBUG
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| 114 | printf("cpu%u: spurious interrupt (intrcv=%#" PRIx64
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| 115 | ", data0=%#" PRIx64 ")\n", CPU->id, intrcv, data0);
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| 116 | #endif
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| 117 | }
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| 118 |
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| 119 | membar();
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| 120 | asi_u64_write(ASI_INTR_RECEIVE, 0, 0);
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| 121 | }
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| 122 |
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| 123 | /** @}
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| 124 | */
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