source: mainline/kernel/arch/sparc64/src/trap/interrupt.c@ 06e1e95

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 06e1e95 was 253f35a1, checked in by Jakub Jermar <jakub@…>, 19 years ago

sparc64 work.

  • Changes to enable userspace keyboard drivers.
  • Fix z8530 initialization (i.e. clear any pending Tx interrupts).
  • Experimental support for framebuffers with inverted colors.
  • Property mode set to 100644
File size: 2.9 KB
Line 
1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup sparc64interrupt
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/interrupt.h>
36#include <arch/trap/interrupt.h>
37#include <interrupt.h>
38#include <arch/drivers/fhc.h>
39#include <typedefs.h>
40#include <arch/types.h>
41#include <debug.h>
42#include <ipc/sysipc.h>
43#include <arch/asm.h>
44#include <arch/barrier.h>
45#include <print.h>
46#include <genarch/kbd/z8530.h>
47
48/** Register Interrupt Level Handler.
49 *
50 * @param n Interrupt Level (1 - 15).
51 * @param name Short descriptive string.
52 * @param f Handler.
53 */
54void interrupt_register(int n, const char *name, iroutine f)
55{
56 ASSERT(n >= IVT_FIRST && n <= IVT_ITEMS);
57
58 exc_register(n - 1, name, f);
59}
60
61/* Reregister irq to be IPC-ready */
62void irq_ipc_bind_arch(unative_t irq)
63{
64#ifdef CONFIG_Z8530
65 z8530_belongs_to_kernel = false;
66#endif
67}
68
69void interrupt(int n, istate_t *istate)
70{
71 uint64_t intrcv;
72 uint64_t data0;
73
74 intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0);
75 data0 = asi_u64_read(ASI_UDB_INTR_R, ASI_UDB_INTR_R_DATA_0);
76
77 switch (data0) {
78#ifdef CONFIG_Z8530
79 case Z8530_INTRCV_DATA0:
80 /*
81 * So far, we know we got this interrupt through the FHC.
82 * Since we don't have enough information about the FHC and
83 * because the interrupt looks like level sensitive,
84 * we cannot handle it by scheduling one of the level
85 * interrupt traps. Call the interrupt handler directly.
86 */
87
88 if (z8530_belongs_to_kernel)
89 z8530_interrupt();
90 else
91 ipc_irq_send_notif(0);
92 fhc_uart_reset();
93 break;
94
95#endif
96 }
97
98 membar();
99 asi_u64_write(ASI_INTR_RECEIVE, 0, 0);
100}
101
102/** @}
103 */
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