| 1 | /*
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| 2 | * Copyright (C) 2005 Jakub Jermar
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup sparc64interrupt
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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| 35 | #include <arch/interrupt.h>
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| 36 | #include <arch/trap/interrupt.h>
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| 37 | #include <interrupt.h>
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| 38 | #include <arch/drivers/fhc.h>
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| 39 | #include <arch/types.h>
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| 40 | #include <debug.h>
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| 41 | #include <ipc/sysipc.h>
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| 42 | #include <arch/asm.h>
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| 43 | #include <arch/barrier.h>
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| 44 |
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| 45 | #include <genarch/kbd/z8530.h>
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| 46 |
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| 47 | /** Register Interrupt Level Handler.
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| 48 | *
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| 49 | * @param n Interrupt Level (1 - 15).
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| 50 | * @param name Short descriptive string.
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| 51 | * @param f Handler.
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| 52 | */
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| 53 | void interrupt_register(int n, const char *name, iroutine f)
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| 54 | {
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| 55 | ASSERT(n >= IVT_FIRST && n <= IVT_ITEMS);
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| 56 |
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| 57 | exc_register(n - 1, name, f);
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| 58 | }
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| 59 |
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| 60 | /* Reregister irq to be IPC-ready */
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| 61 | void irq_ipc_bind_arch(unative_t irq)
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| 62 | {
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| 63 | panic("not implemented\n");
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| 64 | /* TODO */
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| 65 | }
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| 66 |
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| 67 | void interrupt(void)
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| 68 | {
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| 69 | uint64_t intrcv;
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| 70 | uint64_t data0;
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| 71 |
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| 72 | intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0);
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| 73 | data0 = asi_u64_read(ASI_UDB_INTR_R, ASI_UDB_INTR_R_DATA_0);
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| 74 |
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| 75 | switch (data0) {
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| 76 | #ifdef CONFIG_Z8530
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| 77 | case Z8530_INTRCV_DATA0:
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| 78 | /*
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| 79 | * So far, we know we got this interrupt through the FHC.
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| 80 | * Since we don't have enough information about the FHC and
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| 81 | * because the interrupt looks like level sensitive,
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| 82 | * we cannot handle it by scheduling one of the level
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| 83 | * interrupt traps. Call the interrupt handler directly.
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| 84 | */
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| 85 | fhc_uart_reset();
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| 86 | z8530_interrupt();
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| 87 | break;
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| 88 | #endif
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| 89 | }
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| 90 |
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| 91 | membar();
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| 92 | asi_u64_write(ASI_INTR_RECEIVE, 0, 0);
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| 93 | }
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| 94 |
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| 95 | /** @}
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| 96 | */
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