source: mainline/kernel/arch/sparc64/src/sun4v/start.S@ cb7be8f

Last change on this file since cb7be8f was cb7be8f, checked in by Jiří Zárevúcky <zarevucky.jiri@…>, 3 years ago

Update headers in .S files that incorrectly use #-style comments
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File size: 7.7 KB
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1/*
2 * SPDX-FileCopyrightText: 2005 Jakub Jermar
3 * SPDX-FileCopyrightText: 2008 Pavel Rimsky
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include <abi/asmtool.h>
9#include <arch/arch.h>
10#include <arch/stack.h>
11#include <arch/regdef.h>
12#include <arch/context_struct.h>
13#include <arch/sun4v/regdef.h>
14#include <arch/sun4v/hypercall.h>
15#include <arch/sun4v/arch.h>
16#include <arch/sun4v/cpu.h>
17#include <arch/mm/pagesize.h>
18#include <arch/mm/sun4v/tte.h>
19#include <arch/mm/sun4v/mmu.h>
20#include <arch/mm/sun4v/tlb.h>
21
22.register %g2, #scratch
23.register %g3, #scratch
24
25.section K_TEXT_START, "ax"
26
27#define BSP_FLAG 1
28#define PHYSMEM_ADDR_SIZE 56
29
30/*
31 * Flags set in the TTE data entry mapping the kernel.
32 */
33#ifdef CONFIG_VIRT_IDX_DCACHE
34 #define TTE_FLAGS \
35 (1 << TTE_V_SHIFT) \
36 | (1 << TTE_EP_SHIFT) \
37 | (1 << TTE_CP_SHIFT) \
38 | (1 << TTE_CV_SHIFT) \
39 | (1 << TTE_P_SHIFT) \
40 | (1 << TTE_W_SHIFT)
41#else
42 #define TTE_FLAGS \
43 (1 << TTE_V_SHIFT) \
44 | (1 << TTE_EP_SHIFT) \
45 | (1 << TTE_CP_SHIFT) \
46 | (1 << TTE_P_SHIFT) \
47 | (1 << TTE_W_SHIFT)
48#endif
49
50
51/*
52 * Fills a register with a TTE Data item. The item will map the given virtual
53 * address to a real address which will be computed by adding the starting
54 * address of the physical memory to the virtual address.
55 *
56 * parameters:
57 * addr: virtual address to be mapped
58 * rphysmem_start: register containing the starting address
59 * of the physical memory
60 * rtmp1: a register to be used as temporary
61 * rtmp2: a register to be used as temporary
62 * rd: register where the result will be saved
63 *
64 */
65#define TTE_DATA(addr, rphysmem_start, rtmp1, rtmp2, rd) \
66 setx TTE_FLAGS | PAGESIZE_4M, rtmp1, rd; \
67 add rd, rphysmem_start, rd; \
68 setx (addr), rtmp1, rtmp2; \
69 add rd, rtmp2, rd;
70
71/*
72 * Here is where the kernel is passed control from the boot loader.
73 *
74 * The registers are expected to be in this state:
75 * - %o0 starting address of physical memory
76 * + bootstrap processor flag
77 * bits 63...1: physical memory starting address / 2
78 * bit 0: non-zero on BSP processor, zero on AP processors
79 * - %o1 bootinfo structure address (BSP only)
80 *
81 *
82 * Moreover, we depend on boot having established the following environment:
83 * - TLBs are on
84 * - identity mapping for the kernel image
85 *
86 */
87SYMBOL(kernel_image_start)
88 mov BSP_FLAG, %l0
89 and %o0, %l0, %l7 ! l7 <= bootstrap processor?
90 andn %o0, %l0, %l6 ! l6 <= start of physical memory
91 or %o1, %g0, %l1
92
93 ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.
94 srlx %l6, 13, %l5
95
96 ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
97 sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
98 srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5
99
100 /*
101 * Setup basic runtime environment.
102 */
103 wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows
104 wrpr %g0, 0, %canrestore ! get rid of windows we will
105 ! never need again
106 wrpr %g0, 0, %otherwin ! make sure the window state is
107 ! consistent
108 wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window
109 ! traps for kernel
110
111 wrpr %g0, 0, %wstate ! use default spill/fill trap
112
113 wrpr %g0, 0, %tl ! TL = 0, primary context
114 ! register is used
115 wrpr %g0, 0, %gl
116
117 wrpr %g0, PSTATE_PRIV_BIT, %pstate ! disable interrupts and disable
118 ! 32-bit address masking
119
120 wrpr %g0, 0, %pil ! intialize %pil
121
122 /*
123 * Switch to kernel trap table.
124 */
125 sethi %hi(trap_table), %g1
126 wrpr %g1, %lo(trap_table), %tba
127
128 /* Explicitly switch to hypervisor API 1.1. */
129 mov 1, %o0
130 mov 1, %o1
131 mov 1, %o2
132 mov 0, %o3
133 mov 0, %o4
134 mov 0, %o5
135 ta 0xff
136
137 /*
138 * Take over the MMU.
139 */
140
141 ! map kernel in context 1
142 set kernel_load_address, %o0 ! virt. address
143 set 1, %o1 ! context
144 TTE_DATA(kernel_load_address, %l5, %g2, %g3, %o2) ! TTE data
145 set MMU_FLAG_DTLB | MMU_FLAG_ITLB, %o3 ! MMU flags
146 __HYPERCALL_HYPERFAST(MMU_MAP_ADDR)
147
148 ! switch to context 1
149 set 1, %o0
150 set VA_PRIMARY_CONTEXT_REG, %o1
151 stxa %o0, [%o1] ASI_PRIMARY_CONTEXT_REG
152
153 ! demap all in context 0
154 set 0, %o0 ! reserved
155 set 0, %o1 ! reserved
156 set 0, %o2 ! context
157 set MMU_FLAG_DTLB | MMU_FLAG_ITLB, %o3 ! MMU flags
158 __HYPERCALL_FAST(MMU_DEMAP_CTX)
159
160 ! install permanent mapping for kernel in context 0
161 set kernel_load_address, %o0 ! virtual address
162 set 0, %o1 ! context
163 TTE_DATA(kernel_load_address, %l5, %g2, %g3, %o2) ! TTE data
164 set MMU_FLAG_DTLB | MMU_FLAG_ITLB, %o3 ! MMU flags
165 __HYPERCALL_FAST(MMU_MAP_PERM_ADDR)
166
167 ! switch to context 0
168 mov 0, %o0
169 set VA_PRIMARY_CONTEXT_REG, %o1
170 stxa %o0, [%o1] ASI_PRIMARY_CONTEXT_REG
171
172 ! demap all in context 1 (cleanup)
173 set 0, %o0 ! reserved
174 set 0, %o1 ! reserved
175 set 1, %o2 ! context
176 set MMU_FLAG_DTLB | MMU_FLAG_ITLB, %o3 ! MMU flags
177 __HYPERCALL_FAST(MMU_DEMAP_CTX)
178
179 /*
180 * Set CPUID.
181 */
182 __HYPERCALL_FAST(CPU_MYID)
183 mov SCRATCHPAD_CPUID, %g1
184 stxa %o1, [%g1] ASI_SCRATCHPAD
185
186 /*
187 * Set MMU fault status area for the current CPU.
188 */
189 set mmu_fsas, %o0 ! o0 <= addr. of fault status areas array
190 add %o0, %l6, %o0 ! kernel address to real address
191 mulx %o1, MMU_FSA_SIZE, %g1 ! g1 <= offset of current CPU's fault status area
192 add %g1, %o0, %o0 ! o0 <= FSA of the current CPU
193 mov SCRATCHPAD_MMU_FSA, %g1
194 stxa %o0, [%g1] ASI_SCRATCHPAD ! remember MMU fault status area to speed up miss handler
195 __HYPERCALL_FAST(MMU_FAULT_AREA_CONF)
196
197 ! on APs skip executing the following code
198 cmp %l7, 0
199 be %xcc, 1f
200 nop
201
202 /*
203 * Save physmem_base for use by the mm subsystem.
204 * %l6 contains starting physical address
205 */
206 sethi %hi(physmem_base), %l4
207 stx %l6, [%l4 + %lo(physmem_base)]
208
209 /*
210 * Store a template of a TTE Data entry for kernel mappings.
211 * This template will be used from the kernel MMU miss handler.
212 */
213 !TTE_DATA(0, %l5, %g2, %g3, %g1)
214 setx TTE_FLAGS | PAGESIZE_8K, %g2, %g1; \
215 add %g1, %l5, %g1; \
216 set kernel_8k_tlb_data_template, %g4
217 stx %g1, [%g4]
218
219 /*
220 * So far, we have not touched the stack.
221 * It is a good idea to set the kernel stack to a known state now.
222 */
223 sethi %hi(temporary_boot_stack), %sp
224 or %sp, %lo(temporary_boot_stack), %sp
225 sub %sp, STACK_BIAS, %sp
226
227 /*
228 * Call sparc64_pre_main(bootinfo)
229 */
230 call sparc64_pre_main
231 or %l1, %g0, %o0
232
233 /*
234 * Create the first stack frame.
235 */
236 save %sp, -(STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE), %sp
237 flushw
238 add %g0, -STACK_BIAS, %fp
239
240 call main_bsp
241 nop
242
243 /* Not reached. */
244
2450:
246 ba,a %xcc, 0b
247
2481:
249
250#ifdef CONFIG_SMP
251
252 /*
253 * Configure stack for the AP.
254 * The AP is expected to use the stack saved
255 * in the ctx global variable.
256 */
257
258 mov 1, %o0 ! MMU enable flag
259 set mmu_enabled, %o1
260 mov MMU_ENABLE, %o5 ! MMU enable HV call
261 ta 0x80 ! call HV
262
263 mmu_enabled:
264
265 /*
266 * Configure stack for the AP.
267 * The AP is expected to use the stack saved
268 * in the ctx global variable.
269 */
270 set ctx, %g1
271 add %g1, CONTEXT_OFFSET_SP, %g1
272 ldx [%g1], %o6
273
274 /*
275 * Create the first stack frame.
276 */
277 save %sp, -(STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE), %sp
278 flushw
279 add %g0, -STACK_BIAS, %fp
280
281 call main_ap
282 nop
283#endif
284
285 /* Not reached. */
2860:
287 ba,a %xcc, 0b
288
289.section K_DATA_START, "aw", @progbits
290
291#define INITIAL_STACK_SIZE 1024
292
293.align STACK_ALIGNMENT
294 .space INITIAL_STACK_SIZE
295.align STACK_ALIGNMENT
296temporary_boot_stack:
297 .space STACK_WINDOW_SAVE_AREA_SIZE
298
299
300.data
301
302.align 8
303SYMBOL(physmem_base) ! copy of the physical memory base address
304 .quad 0
305
306/*
307 * This variable is used by the fast_data_access_MMU_miss trap handler.
308 * In runtime, it is modified to contain the address of the end of physical
309 * memory.
310 */
311SYMBOL(end_of_identity)
312 .quad -1
313
314SYMBOL(kernel_8k_tlb_data_template)
315 .quad 0
316
317/* MMU fault status areas for all CPUs */
318.align MMU_FSA_ALIGNMENT
319SYMBOL(mmu_fsas)
320 .space (MMU_FSA_SIZE * MAX_NUM_STRANDS)
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