| 1 | #
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| 2 | # Copyright (c) 2005 Jakub Jermar
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| 3 | # Copyright (c) 2008 Pavel Rimsky
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| 4 | # All rights reserved.
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| 5 | #
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| 6 | # Redistribution and use in source and binary forms, with or without
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| 7 | # modification, are permitted provided that the following conditions
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| 8 | # are met:
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| 9 | #
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| 10 | # - Redistributions of source code must retain the above copyright
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| 11 | # notice, this list of conditions and the following disclaimer.
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| 12 | # - Redistributions in binary form must reproduce the above copyright
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| 13 | # notice, this list of conditions and the following disclaimer in the
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| 14 | # documentation and/or other materials provided with the distribution.
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| 15 | # - The name of the author may not be used to endorse or promote products
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| 16 | # derived from this software without specific prior written permission.
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| 17 | #
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| 18 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | #
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| 29 |
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| 30 | #include <arch/arch.h>
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| 31 | #include <arch/stack.h>
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| 32 | #include <arch/regdef.h>
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| 33 | #include <arch/context_offset.h>
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| 34 | #include <arch/sun4v/regdef.h>
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| 35 | #include <arch/sun4v/hypercall.h>
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| 36 | #include <arch/sun4v/arch.h>
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| 37 | #include <arch/sun4v/cpu.h>
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| 38 | #include <arch/mm/pagesize.h>
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| 39 | #include <arch/mm/sun4v/tte.h>
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| 40 | #include <arch/mm/sun4v/mmu.h>
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| 41 | #include <arch/mm/sun4v/tlb.h>
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| 42 |
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| 43 | .register %g2, #scratch
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| 44 | .register %g3, #scratch
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| 45 |
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| 46 | .section K_TEXT_START, "ax"
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| 47 |
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| 48 | #define BSP_FLAG 1
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| 49 | #define PHYSMEM_ADDR_SIZE 56
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| 50 |
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| 51 | /*
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| 52 | * Flags set in the TTE data entry mapping the kernel.
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| 53 | */
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| 54 | #ifdef CONFIG_VIRT_IDX_DCACHE
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| 55 | #define TTE_FLAGS \
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| 56 | (1 << TTE_V_SHIFT) \
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| 57 | | (1 << TTE_EP_SHIFT) \
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| 58 | | (1 << TTE_CP_SHIFT) \
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| 59 | | (1 << TTE_CV_SHIFT) \
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| 60 | | (1 << TTE_P_SHIFT) \
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| 61 | | (1 << TTE_W_SHIFT)
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| 62 | #else
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| 63 | #define TTE_FLAGS \
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| 64 | (1 << TTE_V_SHIFT) \
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| 65 | | (1 << TTE_EP_SHIFT) \
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| 66 | | (1 << TTE_CP_SHIFT) \
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| 67 | | (1 << TTE_P_SHIFT) \
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| 68 | | (1 << TTE_W_SHIFT)
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| 69 | #endif
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| 70 |
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| 71 |
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| 72 | /*
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| 73 | * Fills a register with a TTE Data item. The item will map the given virtual
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| 74 | * address to a real address which will be computed by adding the starting
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| 75 | * address of the physical memory to the virtual address.
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| 76 | *
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| 77 | * parameters:
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| 78 | * addr: virtual address to be mapped
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| 79 | * rphysmem_start: register containing the starting address
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| 80 | * of the physical memory
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| 81 | * rtmp1: a register to be used as temporary
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| 82 | * rtmp2: a register to be used as temporary
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| 83 | * rd: register where the result will be saved
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| 84 | *
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| 85 | */
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| 86 | #define TTE_DATA(addr, rphysmem_start, rtmp1, rtmp2, rd) \
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| 87 | setx TTE_FLAGS | PAGESIZE_4M, rtmp1, rd; \
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| 88 | add rd, rphysmem_start, rd; \
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| 89 | setx (addr), rtmp1, rtmp2; \
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| 90 | add rd, rtmp2, rd;
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| 91 |
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| 92 | /*
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| 93 | * Here is where the kernel is passed control from the boot loader.
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| 94 | *
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| 95 | * The registers are expected to be in this state:
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| 96 | * - %o0 starting address of physical memory
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| 97 | * + bootstrap processor flag
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| 98 | * bits 63...1: physical memory starting address / 2
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| 99 | * bit 0: non-zero on BSP processor, zero on AP processors
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| 100 | * - %o1 bootinfo structure address (BSP only)
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| 101 | *
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| 102 | *
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| 103 | * Moreover, we depend on boot having established the following environment:
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| 104 | * - TLBs are on
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| 105 | * - identity mapping for the kernel image
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| 106 | *
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| 107 | */
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| 108 | .global kernel_image_start
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| 109 | kernel_image_start:
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| 110 | mov BSP_FLAG, %l0
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| 111 | and %o0, %l0, %l7 ! l7 <= bootstrap processor?
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| 112 | andn %o0, %l0, %l6 ! l6 <= start of physical memory
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| 113 | or %o1, %g0, %l1
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| 114 |
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| 115 | ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.
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| 116 | srlx %l6, 13, %l5
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| 117 |
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| 118 | ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
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| 119 | sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
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| 120 | srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5
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| 121 |
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| 122 | /*
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| 123 | * Setup basic runtime environment.
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| 124 | */
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| 125 | wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows
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| 126 | wrpr %g0, 0, %canrestore ! get rid of windows we will
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| 127 | ! never need again
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| 128 | wrpr %g0, 0, %otherwin ! make sure the window state is
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| 129 | ! consistent
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| 130 | wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window
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| 131 | ! traps for kernel
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| 132 |
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| 133 | wrpr %g0, 0, %wstate ! use default spill/fill trap
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| 134 |
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| 135 | wrpr %g0, 0, %tl ! TL = 0, primary context
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| 136 | ! register is used
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| 137 | wrpr %g0, 0, %gl
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| 138 |
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| 139 | wrpr %g0, PSTATE_PRIV_BIT, %pstate ! disable interrupts and disable
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| 140 | ! 32-bit address masking
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| 141 |
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| 142 | wrpr %g0, 0, %pil ! intialize %pil
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| 143 |
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| 144 | /*
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| 145 | * Switch to kernel trap table.
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| 146 | */
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| 147 | sethi %hi(trap_table), %g1
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| 148 | wrpr %g1, %lo(trap_table), %tba
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| 149 |
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| 150 | /* Explicitly switch to hypervisor API 1.1. */
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| 151 | mov 1, %o0
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| 152 | mov 1, %o1
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| 153 | mov 1, %o2
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| 154 | mov 0, %o3
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| 155 | mov 0, %o4
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| 156 | mov 0, %o5
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| 157 | ta 0xff
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| 158 |
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| 159 | /*
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| 160 | * Take over the MMU.
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| 161 | */
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| 162 |
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| 163 | ! map kernel in context 1
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| 164 | set kernel_image_start, %o0 ! virt. address
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| 165 | set 1, %o1 ! context
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| 166 | TTE_DATA(kernel_image_start, %l5, %g2, %g3, %o2) ! TTE data
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| 167 | set MMU_FLAG_DTLB | MMU_FLAG_ITLB, %o3 ! MMU flags
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| 168 | __HYPERCALL_HYPERFAST(MMU_MAP_ADDR)
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| 169 |
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| 170 | ! switch to context 1
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| 171 | set 1, %o0
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| 172 | set VA_PRIMARY_CONTEXT_REG, %o1
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| 173 | stxa %o0, [%o1] ASI_PRIMARY_CONTEXT_REG
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| 174 |
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| 175 | ! demap all in context 0
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| 176 | set 0, %o0 ! reserved
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| 177 | set 0, %o1 ! reserved
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| 178 | set 0, %o2 ! context
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| 179 | set MMU_FLAG_DTLB | MMU_FLAG_ITLB, %o3 ! MMU flags
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| 180 | __HYPERCALL_FAST(MMU_DEMAP_CTX)
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| 181 |
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| 182 | ! install permanent mapping for kernel in context 0
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| 183 | set kernel_image_start, %o0 ! virtual address
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| 184 | set 0, %o1 ! context
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| 185 | TTE_DATA(kernel_image_start, %l5, %g2, %g3, %o2) ! TTE data
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| 186 | set MMU_FLAG_DTLB | MMU_FLAG_ITLB, %o3 ! MMU flags
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| 187 | __HYPERCALL_FAST(MMU_MAP_PERM_ADDR)
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| 188 |
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| 189 | ! switch to context 0
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| 190 | mov 0, %o0
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| 191 | set VA_PRIMARY_CONTEXT_REG, %o1
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| 192 | stxa %o0, [%o1] ASI_PRIMARY_CONTEXT_REG
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| 193 |
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| 194 | ! demap all in context 1 (cleanup)
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| 195 | set 0, %o0 ! reserved
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| 196 | set 0, %o1 ! reserved
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| 197 | set 1, %o2 ! context
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| 198 | set MMU_FLAG_DTLB | MMU_FLAG_ITLB, %o3 ! MMU flags
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| 199 | __HYPERCALL_FAST(MMU_DEMAP_CTX)
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| 200 |
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| 201 | /*
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| 202 | * Set CPUID.
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| 203 | */
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| 204 | __HYPERCALL_FAST(CPU_MYID)
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| 205 | mov SCRATCHPAD_CPUID, %g1
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| 206 | stxa %o1, [%g1] ASI_SCRATCHPAD
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| 207 |
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| 208 | /*
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| 209 | * Set MMU fault status area for the current CPU.
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| 210 | */
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| 211 | set mmu_fsas, %o0 ! o0 <= addr. of fault status areas array
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| 212 | add %o0, %l6, %o0 ! kernel address to real address
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| 213 | mulx %o1, MMU_FSA_SIZE, %g1 ! g1 <= offset of current CPU's fault status area
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| 214 | add %g1, %o0, %o0 ! o0 <= FSA of the current CPU
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| 215 | mov SCRATCHPAD_MMU_FSA, %g1
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| 216 | stxa %o0, [%g1] ASI_SCRATCHPAD ! remember MMU fault status area to speed up miss handler
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| 217 | __HYPERCALL_FAST(MMU_FAULT_AREA_CONF)
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| 218 |
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| 219 | ! on APs skip executing the following code
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| 220 | cmp %l7, 0
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| 221 | be %xcc, 1f
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| 222 | nop
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| 223 |
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| 224 | /*
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| 225 | * Save physmem_base for use by the mm subsystem.
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| 226 | * %l6 contains starting physical address
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| 227 | */
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| 228 | sethi %hi(physmem_base), %l4
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| 229 | stx %l6, [%l4 + %lo(physmem_base)]
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| 230 |
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| 231 | /*
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| 232 | * Store a template of a TTE Data entry for kernel mappings.
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| 233 | * This template will be used from the kernel MMU miss handler.
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| 234 | */
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| 235 | !TTE_DATA(0, %l5, %g2, %g3, %g1)
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| 236 | setx TTE_FLAGS | PAGESIZE_8K, %g2, %g1; \
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| 237 | add %g1, %l5, %g1; \
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| 238 | set kernel_8k_tlb_data_template, %g4
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| 239 | stx %g1, [%g4]
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| 240 |
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| 241 | /*
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| 242 | * So far, we have not touched the stack.
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| 243 | * It is a good idea to set the kernel stack to a known state now.
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| 244 | */
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| 245 | sethi %hi(temporary_boot_stack), %sp
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| 246 | or %sp, %lo(temporary_boot_stack), %sp
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| 247 | sub %sp, STACK_BIAS, %sp
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| 248 |
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| 249 | /*
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| 250 | * Call arch_pre_main(bootinfo)
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| 251 | */
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| 252 | call arch_pre_main
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| 253 | or %l1, %g0, %o0
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| 254 |
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| 255 | /*
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| 256 | * Create the first stack frame.
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| 257 | */
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| 258 | save %sp, -(STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE), %sp
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| 259 | flushw
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| 260 | add %g0, -STACK_BIAS, %fp
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| 261 |
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| 262 | call main_bsp
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| 263 | nop
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| 264 |
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| 265 | /* Not reached. */
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| 266 |
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| 267 | 0:
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| 268 | ba,a %xcc, 0b
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| 269 |
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| 270 | 1:
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| 271 |
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| 272 | #ifdef CONFIG_SMP
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| 273 |
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| 274 | /*
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| 275 | * Configure stack for the AP.
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| 276 | * The AP is expected to use the stack saved
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| 277 | * in the ctx global variable.
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| 278 | */
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| 279 |
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| 280 | mov 1, %o0 ! MMU enable flag
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| 281 | set mmu_enabled, %o1
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| 282 | mov MMU_ENABLE, %o5 ! MMU enable HV call
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| 283 | ta 0x80 ! call HV
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| 284 |
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| 285 | mmu_enabled:
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| 286 |
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| 287 | /*
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| 288 | * Configure stack for the AP.
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| 289 | * The AP is expected to use the stack saved
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| 290 | * in the ctx global variable.
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| 291 | */
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| 292 | set ctx, %g1
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| 293 | add %g1, OFFSET_SP, %g1
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| 294 | ldx [%g1], %o6
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| 295 |
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| 296 | /*
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| 297 | * Create the first stack frame.
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| 298 | */
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| 299 | save %sp, -(STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE), %sp
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| 300 | flushw
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| 301 | add %g0, -STACK_BIAS, %fp
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| 302 |
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| 303 | call main_ap
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| 304 | nop
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| 305 | #endif
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| 306 |
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| 307 | /* Not reached. */
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| 308 | 0:
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| 309 | ba,a %xcc, 0b
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| 310 |
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| 311 | .align 8
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| 312 | .global temp_cpu_mondo_handler
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| 313 | temp_cpu_mondo_handler:
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| 314 |
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| 315 | set 0x3c, %o0
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| 316 | set 0x15, %o5
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| 317 | ta 0x80
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| 318 |
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| 319 | mov 0, %o0
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| 320 | setx before_ap_boots, %g1, %o1
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| 321 | setx 0x80400000, %g1, %o2
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| 322 | add %o1, %o2, %o1
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| 323 | __HYPERCALL_FAST(MMU_ENABLE)
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| 324 |
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| 325 | before_ap_boots:
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| 326 | setx 0x80400000, %g0, %o0
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| 327 | ba,a %xcc, kernel_image_start
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| 328 |
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| 329 | .section K_DATA_START, "aw", @progbits
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| 330 |
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| 331 | #define INITIAL_STACK_SIZE 1024
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| 332 |
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| 333 | .align STACK_ALIGNMENT
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| 334 | .space INITIAL_STACK_SIZE
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| 335 | .align STACK_ALIGNMENT
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| 336 | temporary_boot_stack:
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| 337 | .space STACK_WINDOW_SAVE_AREA_SIZE
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| 338 |
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| 339 |
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| 340 | .data
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| 341 |
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| 342 | .align 8
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| 343 | .global physmem_base ! copy of the physical memory base address
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| 344 | physmem_base:
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| 345 | .quad 0
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| 346 |
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| 347 | .global kernel_8k_tlb_data_template
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| 348 | kernel_8k_tlb_data_template:
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| 349 | .quad 0
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| 350 |
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| 351 | /* MMU fault status areas for all CPUs */
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| 352 | .align MMU_FSA_ALIGNMENT
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| 353 | .global mmu_fsas
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| 354 | mmu_fsas:
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| 355 | .space (MMU_FSA_SIZE * MAX_NUM_STRANDS)
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