source: mainline/kernel/arch/sparc64/src/sun4v/start.S@ 86018c1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 86018c1 was f238e86, checked in by Pavel Rimsky <pavel@…>, 16 years ago

Both sun4u and sun4v are compilable, sun4u feature-complete, sun4v reaches (at least) version_print.
  • Property mode set to 100644
File size: 8.8 KB
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[f238e86]1#
2# Copyright (c) 2005 Jakub Jermar
3# Copyright (c) 2008 Pavel Rimsky
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions
8# are met:
9#
10# - Redistributions of source code must retain the above copyright
11# notice, this list of conditions and the following disclaimer.
12# - Redistributions in binary form must reproduce the above copyright
13# notice, this list of conditions and the following disclaimer in the
14# documentation and/or other materials provided with the distribution.
15# - The name of the author may not be used to endorse or promote products
16# derived from this software without specific prior written permission.
17#
18# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29
30#include <arch/arch.h>
31#include <arch/stack.h>
32#include <arch/context_offset.h>
33#include <arch/sun4v/regdef.h>
34#include <arch/sun4v/hypercall.h>
35#include <arch/sun4v/arch.h>
36#include <arch/sun4v/cpu.h>
37#include <arch/mm/pagesize.h>
38#include <arch/mm/sun4v/tte.h>
39#include <arch/mm/sun4v/mmu.h>
40#include <arch/mm/sun4v/tlb.h>
41
42.register %g2, #scratch
43.register %g3, #scratch
44
45.section K_TEXT_START, "ax"
46
47#define BSP_FLAG 1
48#define PHYSMEM_ADDR_SIZE 56
49
50/*
51 * Flags set in the TTE data entry mapping the kernel.
52 */
53#ifdef CONFIG_VIRT_IDX_DCACHE
54 #define TTE_FLAGS \
55 (1 << TTE_V_SHIFT) \
56 | (1 << TTE_EP_SHIFT) \
57 | (1 << TTE_CP_SHIFT) \
58 | (1 << TTE_CV_SHIFT) \
59 | (1 << TTE_P_SHIFT) \
60 | (1 << TTE_W_SHIFT)
61#else
62 #define TTE_FLAGS \
63 (1 << TTE_V_SHIFT) \
64 | (1 << TTE_EP_SHIFT) \
65 | (1 << TTE_CP_SHIFT) \
66 | (1 << TTE_P_SHIFT) \
67 | (1 << TTE_W_SHIFT)
68#endif
69
70
71/*
72 * Fills a register with a TTE Data item. The item will map the given virtual
73 * address to a real address which will be computed by adding the starting
74 * address of the physical memory to the virtual address.
75 *
76 * parameters:
77 * addr: virtual address to be mapped
78 * rphysmem_start: register containing the starting address of the
79 * physical memory
80 * rtmp1: a register to be used as temporary
81 * rtmp2: a register to be used as temporary
82 * rd: register where the result will be saved
83 */
84#define TTE_DATA(addr, rphysmem_start, rtmp1, rtmp2, rd) \
85 setx TTE_FLAGS | PAGESIZE_4M, rtmp1, rd; \
86 add rd, rphysmem_start, rd; \
87 setx (addr), rtmp1, rtmp2; \
88 add rd, rtmp2, rd;
89
90/*
91 * Here is where the kernel is passed control from the boot loader.
92 *
93 * The registers are expected to be in this state:
94 * - %o0 starting address of physical memory + bootstrap processor flag
95 * bits 63...1: physical memory starting address / 2
96 * bit 0: non-zero on BSP processor, zero on AP processors
97 * - %o1 bootinfo structure address (BSP only)
98 * - %o2 bootinfo structure size (BSP only)
99 *
100 * Moreover, we depend on boot having established the following environment:
101 * - TLBs are on
102 * - identity mapping for the kernel image
103 */
104.global kernel_image_start
105kernel_image_start:
106 mov BSP_FLAG, %l0
107 and %o0, %l0, %l7 ! l7 <= bootstrap processor?
108 andn %o0, %l0, %l6 ! l6 <= start of physical memory
109 or %o1, %g0, %l1
110 or %o2, %g0, %l2
111
112 ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.
113 srlx %l6, 13, %l5
114
115 ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
116 sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
117 srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5
118
119 /*
120 * Setup basic runtime environment.
121 */
122 wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows
123 wrpr %g0, 0, %canrestore ! get rid of windows we will
124 ! never need again
125 wrpr %g0, 0, %otherwin ! make sure the window state is
126 ! consistent
127 wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window
128 ! traps for kernel
129
130 wrpr %g0, 0, %wstate ! use default spill/fill trap
131
132 wrpr %g0, 0, %tl ! TL = 0, primary context
133 ! register is used
134 wrpr %g0, 0, %gl
135
136 wrpr %g0, PSTATE_PRIV_BIT, %pstate ! disable interrupts and disable
137 ! 32-bit address masking
138
139 wrpr %g0, 0, %pil ! intialize %pil
140
141 /*
142 * Switch to kernel trap table.
143 */
144 sethi %hi(trap_table), %g1
145 wrpr %g1, %lo(trap_table), %tba
146
147 /* Explicitly switch to hypervisor API 1.1. */
148 mov 1, %o0
149 mov 1, %o1
150 mov 1, %o2
151 mov 0, %o3
152 mov 0, %o4
153 mov 0, %o5
154 ta 0xff
155 nop
156
157 /*
158 * Take over the MMU.
159 */
160
161 ! map kernel in context 1
162 set kernel_image_start, %o0 ! virt. address
163 set 1, %o1 ! context
164 TTE_DATA(kernel_image_start, %l5, %g2, %g3, %o2) ! TTE data
165 set MMU_FLAG_DTLB | MMU_FLAG_ITLB, %o3 ! MMU flags
166 __HYPERCALL_HYPERFAST(MMU_MAP_ADDR)
167
168 ! switch to context 1
169 set 1, %o0
170 set VA_PRIMARY_CONTEXT_REG, %o1
171 stxa %o0, [%o1] ASI_PRIMARY_CONTEXT_REG
172
173 ! demap all in context 0
174 set 0, %o0 ! reserved
175 set 0, %o1 ! reserved
176 set 0, %o2 ! context
177 set MMU_FLAG_DTLB | MMU_FLAG_ITLB, %o3 ! MMU flags
178 __HYPERCALL_FAST(MMU_DEMAP_CTX)
179
180 ! install permanent mapping for kernel in context 0
181 set kernel_image_start, %o0 ! virtual address
182 set 0, %o1 ! context
183 TTE_DATA(kernel_image_start, %l5, %g2, %g3, %o2) ! TTE data
184 set MMU_FLAG_DTLB | MMU_FLAG_ITLB, %o3 ! MMU flags
185 __HYPERCALL_FAST(MMU_MAP_PERM_ADDR)
186
187 ! switch to context 0
188 mov 0, %o0
189 set VA_PRIMARY_CONTEXT_REG, %o1
190 stxa %o0, [%o1] ASI_PRIMARY_CONTEXT_REG
191
192 ! demap all in context 1 (cleanup)
193 set 0, %o0 ! reserved
194 set 0, %o1 ! reserved
195 set 1, %o2 ! context
196 set MMU_FLAG_DTLB | MMU_FLAG_ITLB, %o3 ! MMU flags
197 __HYPERCALL_FAST(MMU_DEMAP_CTX)
198
199 /*
200 * Set CPUID.
201 */
202 __HYPERCALL_FAST(CPU_MYID)
203 mov SCRATCHPAD_CPUID, %g1
204 stxa %o1, [%g1] ASI_SCRATCHPAD
205
206 /*
207 * Set MMU fault status area for the current CPU.
208 */
209 set mmu_fsas, %o0 ! o0 <= addr. of fault status areas array
210 add %o0, %l6, %o0 ! kernel address to real address
211 mulx %o1, MMU_FSA_SIZE, %g1 ! g1 <= offset of current CPU's fault status area
212 add %g1, %o0, %o0 ! o0 <= FSA of the current CPU
213 mov SCRATCHPAD_MMU_FSA, %g1
214 stxa %o0, [%g1] ASI_SCRATCHPAD ! remember MMU fault status area to speed up miss handler
215 __HYPERCALL_FAST(MMU_FAULT_AREA_CONF)
216
217 ! on APs skip executing the following code
218 cmp %l7, 0
219 be 1f
220 nop
221
222 /*
223 * Save physmem_base for use by the mm subsystem.
224 * %l6 contains starting physical address
225 */
226 sethi %hi(physmem_base), %l4
227 stx %l6, [%l4 + %lo(physmem_base)]
228
229 /*
230 * Store a template of a TTE Data entry for kernel mappings.
231 * This template will be used from the kernel MMU miss handler.
232 */
233 !TTE_DATA(0, %l5, %g2, %g3, %g1)
234 setx TTE_FLAGS | PAGESIZE_8K, %g2, %g1; \
235 add %g1, %l5, %g1; \
236 set kernel_8k_tlb_data_template, %g4
237 stx %g1, [%g4]
238
239 /*
240 * So far, we have not touched the stack.
241 * It is a good idea to set the kernel stack to a known state now.
242 */
243 sethi %hi(temporary_boot_stack), %sp
244 or %sp, %lo(temporary_boot_stack), %sp
245 sub %sp, STACK_BIAS, %sp
246
247 or %l1, %g0, %o1
248 or %l2, %g0, %o2
249 sethi %hi(bootinfo), %o0
250 call memcpy ! copy bootinfo
251 or %o0, %lo(bootinfo), %o0
252
253 call arch_pre_main
254 nop
255
256 call main_bsp
257 nop
258
259 /* Not reached. */
260
2610:
262 ba 0b
263 nop
264
2651:
266
267#ifdef CONFIG_SMP
268
269 /*
270 * Configure stack for the AP.
271 * The AP is expected to use the stack saved
272 * in the ctx global variable.
273 */
274
275 mov 1, %o0 ! MMU enable flag
276 set mmu_enabled, %o1
277 mov MMU_ENABLE, %o5 ! MMU enable HV call
278 ta 0x80 ! call HV
279
280 mmu_enabled:
281
282 /*
283 * Configure stack for the AP.
284 * The AP is expected to use the stack saved
285 * in the ctx global variable.
286 */
287 set ctx, %g1
288 add %g1, OFFSET_SP, %g1
289 ldx [%g1], %o6
290
291 call main_ap
292 nop
293#endif
294
295 /* Not reached. */
2960:
297 ba 0b
298 nop
299
300.align 8
301.global temp_cpu_mondo_handler
302temp_cpu_mondo_handler:
303
304 set 0x3c, %o0
305 set 0x15, %o5
306 ta 0x80
307
308 mov 0, %o0
309 setx before_ap_boots, %g1, %o1
310 setx 0x80400000, %g1, %o2
311 add %o1, %o2, %o1
312 __HYPERCALL_FAST(MMU_ENABLE)
313
314before_ap_boots:
315 setx 0x80400000, %g0, %o0
316 ba kernel_image_start
317 nop
318
319.section K_DATA_START, "aw", @progbits
320
321#define INITIAL_STACK_SIZE 1024
322
323.align STACK_ALIGNMENT
324 .space INITIAL_STACK_SIZE
325.align STACK_ALIGNMENT
326temporary_boot_stack:
327 .space STACK_WINDOW_SAVE_AREA_SIZE
328
329
330.data
331
332.align 8
333.global physmem_base ! copy of the physical memory base address
334physmem_base:
335 .quad 0
336
337.global kernel_8k_tlb_data_template
338kernel_8k_tlb_data_template:
339 .quad 0
340
341/* MMU fault status areas for all CPUs */
342.align MMU_FSA_ALIGNMENT
343.global mmu_fsas
344mmu_fsas:
345 .space (MMU_FSA_SIZE * MAX_NUM_STRANDS)
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