source: mainline/kernel/arch/sparc64/src/sun4u/asm.S@ 86018c1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 86018c1 was 18baf9c0, checked in by Pavel Rimsky <pavel@…>, 16 years ago

Sources forked into sun4u and sun4v versions such that sun4u and sun4v have separate switch_to_userspace routines.

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File size: 3.4 KB
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1#
2# Copyright (c) 2005 Jakub Jermar
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29#include <arch/arch.h>
30#include <arch/stack.h>
31#include <arch/regdef.h>
32#include <arch/mm/mmu.h>
33
34.text
35
36.register %g2, #scratch
37.register %g3, #scratch
38
39.macro WRITE_ALTERNATE_REGISTER reg, bit
40 rdpr %pstate, %g1 ! save PSTATE.PEF
41 wrpr %g0, (\bit | PSTATE_PRIV_BIT), %pstate
42 mov %o0, \reg
43 wrpr %g0, PSTATE_PRIV_BIT, %pstate
44 retl
45 wrpr %g1, 0, %pstate ! restore PSTATE.PEF
46.endm
47
48.macro READ_ALTERNATE_REGISTER reg, bit
49 rdpr %pstate, %g1 ! save PSTATE.PEF
50 wrpr %g0, (\bit | PSTATE_PRIV_BIT), %pstate
51 mov \reg, %o0
52 wrpr %g0, PSTATE_PRIV_BIT, %pstate
53 retl
54 wrpr %g1, 0, %pstate ! restore PSTATE.PEF
55.endm
56
57.global write_to_ag_g6
58write_to_ag_g6:
59 WRITE_ALTERNATE_REGISTER %g6, PSTATE_AG_BIT
60
61.global write_to_ag_g7
62write_to_ag_g7:
63 WRITE_ALTERNATE_REGISTER %g7, PSTATE_AG_BIT
64
65.global write_to_ig_g6
66write_to_ig_g6:
67 WRITE_ALTERNATE_REGISTER %g6, PSTATE_IG_BIT
68
69.global read_from_ag_g7
70read_from_ag_g7:
71 READ_ALTERNATE_REGISTER %g7, PSTATE_AG_BIT
72
73/** Switch to userspace.
74 *
75 * %o0 Userspace entry address.
76 * %o1 Userspace stack pointer address.
77 * %o2 Userspace address of uarg structure.
78 */
79.global switch_to_userspace
80switch_to_userspace:
81 save %o1, -(STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE), %sp
82 flushw
83 wrpr %g0, 0, %cleanwin ! avoid information leak
84
85 mov %i2, %o0 ! uarg
86 xor %o1, %o1, %o1 ! %o1 is defined to hold pcb_ptr
87 ! set it to 0
88
89 clr %i2
90 clr %i3
91 clr %i4
92 clr %i5
93 clr %i6
94
95 wrpr %g0, 1, %tl ! enforce mapping via nucleus
96
97 rdpr %cwp, %g1
98 wrpr %g1, TSTATE_IE_BIT, %tstate
99 wrpr %i0, 0, %tnpc
100
101 /*
102 * Set primary context according to secondary context.
103 * Secondary context has been already installed by
104 * higher-level functions.
105 */
106 wr %g0, ASI_DMMU, %asi
107 ldxa [VA_SECONDARY_CONTEXT_REG] %asi, %g1
108 stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi
109 flush %i7
110
111 /*
112 * Spills and fills will be handled by the userspace handlers.
113 */
114 wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(1), %wstate
115
116 done ! jump to userspace
117
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