source: mainline/kernel/arch/sparc64/src/start.S@ 8440473

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 8440473 was 8440473, checked in by Jakub Jermar <jakub@…>, 19 years ago

Minor changes. Some coding style fixes and also a type (tee vs. tree).
One AS → as change.
  • Property mode set to 100644
File size: 8.3 KB
Line 
1#
2# Copyright (C) 2005 Jakub Jermar
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29#include <arch/arch.h>
30#include <arch/regdef.h>
31#include <arch/boot/boot.h>
32#include <arch/stack.h>
33
34#include <arch/mm/mmu.h>
35#include <arch/mm/tlb.h>
36#include <arch/mm/tte.h>
37
38#ifdef CONFIG_SMP
39#include <arch/context_offset.h>
40#endif
41
42.register %g2, #scratch
43.register %g3, #scratch
44
45.section K_TEXT_START, "ax"
46
47/*
48 * Here is where the kernel is passed control
49 * from the boot loader.
50 *
51 * The registers are expected to be in this state:
52 * - %o0 non-zero for the bootstrap processor, zero for application/secondary processors
53 * - %o1 bootinfo structure address
54 * - %o2 bootinfo structure size
55 *
56 * Moreover, we depend on boot having established the
57 * following environment:
58 * - TLBs are on
59 * - identity mapping for the kernel image
60 */
61
62.global kernel_image_start
63kernel_image_start:
64 mov %o0, %l7
65
66 /*
67 * Setup basic runtime environment.
68 */
69
70 wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows
71 wrpr %g0, 0, %canrestore ! get rid of windows we will never need again
72 wrpr %g0, 0, %otherwin ! make sure the window state is consistent
73 wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window traps for kernel
74
75 wrpr %g0, 0, %tl ! TL = 0, primary context register is used
76
77 wrpr %g0, PSTATE_PRIV_BIT, %pstate ! Disable interrupts and disable 32-bit address masking.
78
79 wrpr %g0, 0, %pil ! intialize %pil
80
81 /*
82 * Switch to kernel trap table.
83 */
84 sethi %hi(trap_table), %g1
85 wrpr %g1, %lo(trap_table), %tba
86
87 /*
88 * Take over the DMMU by installing global locked
89 * TTE entry identically mapping the first 4M
90 * of memory.
91 *
92 * In case of DMMU, no FLUSH instructions need to be
93 * issued. Because of that, the old DTLB contents can
94 * be demapped pretty straightforwardly and without
95 * causing any traps.
96 */
97
98 wr %g0, ASI_DMMU, %asi
99
100#define SET_TLB_DEMAP_CMD(r1, context_id) \
101 set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) | (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1
102
103 ! demap context 0
104 SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
105 stxa %g0, [%g1] ASI_DMMU_DEMAP
106 membar #Sync
107
108#define SET_TLB_TAG(r1, context) \
109 set VMA | (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
110
111 ! write DTLB tag
112 SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
113 stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
114 membar #Sync
115
116#define SET_TLB_DATA(r1, r2, imm) \
117 set TTE_CV | TTE_CP | TTE_P | LMA | imm, %r1; \
118 set PAGESIZE_4M, %r2; \
119 sllx %r2, TTE_SIZE_SHIFT, %r2; \
120 or %r1, %r2, %r1; \
121 mov 1, %r2; \
122 sllx %r2, TTE_V_SHIFT, %r2; \
123 or %r1, %r2, %r1;
124
125 ! write DTLB data and install the kernel mapping
126 SET_TLB_DATA(g1, g2, TTE_L | TTE_W) ! use non-global mapping
127 stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
128 membar #Sync
129
130 /*
131 * Because we cannot use global mappings (because we want to
132 * have separate 64-bit address spaces for both the kernel
133 * and the userspace), we prepare the identity mapping also in
134 * context 1. This step is required by the
135 * code installing the ITLB mapping.
136 */
137 ! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)
138 SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
139 stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
140 membar #Sync
141
142 ! write DTLB data and install the kernel mapping in context 1
143 SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping
144 stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
145 membar #Sync
146
147 /*
148 * Now is time to take over the IMMU.
149 * Unfortunatelly, it cannot be done as easily as the DMMU,
150 * because the IMMU is mapping the code it executes.
151 *
152 * [ Note that brave experiments with disabling the IMMU
153 * and using the DMMU approach failed after a dozen
154 * of desparate days with only little success. ]
155 *
156 * The approach used here is inspired from OpenBSD.
157 * First, the kernel creates IMMU mapping for itself
158 * in context 1 (MEM_CONTEXT_TEMP) and switches to
159 * it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
160 * afterwards and replaced with the kernel permanent
161 * mapping. Finally, the kernel switches back to
162 * context 0 and demaps context 1.
163 *
164 * Moreover, the IMMU requires use of the FLUSH instructions.
165 * But that is OK because we always use operands with
166 * addresses already mapped by the taken over DTLB.
167 */
168
169 set kernel_image_start, %g5
170
171 ! write ITLB tag of context 1
172 SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
173 mov VA_DMMU_TAG_ACCESS, %g2
174 stxa %g1, [%g2] ASI_IMMU
175 flush %g5
176
177 ! write ITLB data and install the temporary mapping in context 1
178 SET_TLB_DATA(g1, g2, 0) ! use non-global mapping
179 stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
180 flush %g5
181
182 ! switch to context 1
183 mov MEM_CONTEXT_TEMP, %g1
184 stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
185 flush %g5
186
187 ! demap context 0
188 SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
189 stxa %g0, [%g1] ASI_IMMU_DEMAP
190 flush %g5
191
192 ! write ITLB tag of context 0
193 SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
194 mov VA_DMMU_TAG_ACCESS, %g2
195 stxa %g1, [%g2] ASI_IMMU
196 flush %g5
197
198 ! write ITLB data and install the permanent kernel mapping in context 0
199 SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping
200 stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
201 flush %g5
202
203 ! enter nucleus - using context 0
204 wrpr %g0, 1, %tl
205
206 ! demap context 1
207 SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
208 stxa %g0, [%g1] ASI_IMMU_DEMAP
209 flush %g5
210
211 ! set context 0 in the primary context register
212 stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
213 flush %g5
214
215 ! leave nucleus - using primary context, i.e. context 0
216 wrpr %g0, 0, %tl
217
218 brz %l7, 1f ! skip if you are not the bootstrap CPU
219 nop
220
221 /*
222 * So far, we have not touched the stack.
223 * It is a good idead to set the kernel stack to a known state now.
224 */
225 sethi %hi(temporary_boot_stack), %sp
226 or %sp, %lo(temporary_boot_stack), %sp
227 sub %sp, STACK_BIAS, %sp
228
229 sethi %hi(bootinfo), %o0
230 call memcpy ! copy bootinfo
231 or %o0, %lo(bootinfo), %o0
232
233 call arch_pre_main
234 nop
235
236 call main_bsp
237 nop
238
239 /* Not reached. */
240
2410:
242 ba 0b
243 nop
244
245
246 /*
247 * Read MID from the processor.
248 */
2491:
250 ldxa [%g0] ASI_UPA_CONFIG, %g1
251 srlx %g1, UPA_CONFIG_MID_SHIFT, %g1
252 and %g1, UPA_CONFIG_MID_MASK, %g1
253
254#ifdef CONFIG_SMP
255 /*
256 * Active loop for APs until the BSP picks them up.
257 * A processor cannot leave the loop until the
258 * global variable 'waking_up_mid' equals its
259 * MID.
260 */
261 set waking_up_mid, %g2
2622:
263 ldx [%g2], %g3
264 cmp %g3, %g1
265 bne 2b
266 nop
267
268 /*
269 * Configure stack for the AP.
270 * The AP is expected to use the stack saved
271 * in the ctx global variable.
272 */
273 set ctx, %g1
274 add %g1, OFFSET_SP, %g1
275 ldx [%g1], %o6
276
277 call main_ap
278 nop
279
280 /* Not reached. */
281#endif
282
2830:
284 ba 0b
285 nop
286
287
288.section K_DATA_START, "aw", @progbits
289
290/*
291 * Create small stack to be used by the bootstrap processor.
292 * It is going to be used only for a very limited period of
293 * time, but we switch to it anyway, just to be sure we are
294 * properly initialized.
295 *
296 * What is important is that this piece of memory is covered
297 * by the 4M DTLB locked entry and therefore there will be
298 * no surprises like deadly combinations of spill trap and
299 * and TLB miss on the stack address.
300 */
301
302#define INITIAL_STACK_SIZE 1024
303
304.align STACK_ALIGNMENT
305.space INITIAL_STACK_SIZE
306.align STACK_ALIGNMENT
307temporary_boot_stack:
308.space STACK_WINDOW_SAVE_AREA_SIZE
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