source: mainline/kernel/arch/sparc64/src/start.S@ 4b43f86

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 4b43f86 was 92778f2, checked in by Jakub Jermar <jakub@…>, 19 years ago

Initial support for handling illegal virtual aliases on sparc64.
  • Property mode set to 100644
File size: 10.0 KB
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1#
2# Copyright (C) 2005 Jakub Jermar
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29#include <arch/arch.h>
30#include <arch/regdef.h>
31#include <arch/boot/boot.h>
32#include <arch/stack.h>
33
34#include <arch/mm/mmu.h>
35#include <arch/mm/tlb.h>
36#include <arch/mm/tte.h>
37
38#ifdef CONFIG_SMP
39#include <arch/context_offset.h>
40#endif
41
42.register %g2, #scratch
43.register %g3, #scratch
44
45.section K_TEXT_START, "ax"
46
47#define BSP_FLAG 1
48
49/*
50 * Here is where the kernel is passed control from the boot loader.
51 *
52 * The registers are expected to be in this state:
53 * - %o0 starting address of physical memory + bootstrap processor flag
54 * bits 63...1: physical memory starting address / 2
55 * bit 0: non-zero on BSP processor, zero on AP processors
56 * - %o1 bootinfo structure address (BSP only)
57 * - %o2 bootinfo structure size (BSP only)
58 *
59 * Moreover, we depend on boot having established the following environment:
60 * - TLBs are on
61 * - identity mapping for the kernel image
62 */
63
64.global kernel_image_start
65kernel_image_start:
66 mov BSP_FLAG, %l0
67 and %o0, %l0, %l7 ! l7 <= bootstrap processor?
68 andn %o0, %l0, %l6 ! l6 <= start of physical memory
69
70 ! Get bits 40:13 of physmem_base.
71 srlx %l6, 13, %l5
72 sllx %l5, 13 + (63 - 40), %l5
73 srlx %l5, 63 - 40, %l5 ! l5 <= physmem_base[40:13]
74
75 /*
76 * Setup basic runtime environment.
77 */
78
79 wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows
80 wrpr %g0, 0, %canrestore ! get rid of windows we will never need again
81 wrpr %g0, 0, %otherwin ! make sure the window state is consistent
82 wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window traps for kernel
83
84 wrpr %g0, 0, %tl ! TL = 0, primary context register is used
85
86 wrpr %g0, PSTATE_PRIV_BIT, %pstate ! Disable interrupts and disable 32-bit address masking.
87
88 wrpr %g0, 0, %pil ! intialize %pil
89
90 /*
91 * Switch to kernel trap table.
92 */
93 sethi %hi(trap_table), %g1
94 wrpr %g1, %lo(trap_table), %tba
95
96 /*
97 * Take over the DMMU by installing global locked
98 * TTE entry identically mapping the first 4M
99 * of memory.
100 *
101 * In case of DMMU, no FLUSH instructions need to be
102 * issued. Because of that, the old DTLB contents can
103 * be demapped pretty straightforwardly and without
104 * causing any traps.
105 */
106
107 wr %g0, ASI_DMMU, %asi
108
109#define SET_TLB_DEMAP_CMD(r1, context_id) \
110 set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) | (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1
111
112 ! demap context 0
113 SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
114 stxa %g0, [%g1] ASI_DMMU_DEMAP
115 membar #Sync
116
117#define SET_TLB_TAG(r1, context) \
118 set VMA | (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
119
120 ! write DTLB tag
121 SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
122 stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
123 membar #Sync
124
125#ifdef CONFIG_VIRT_IDX_DCACHE
126#define TTE_LOW_DATA(imm) (TTE_CP | TTE_CV | TTE_P | LMA | (imm))
127#else /* CONFIG_VIRT_IDX_DCACHE */
128#define TTE_LOW_DATA(imm) (TTE_CP | TTE_P | LMA | (imm))
129#endif /* CONFIG_VIRT_IDX_DCACHE */
130
131#define SET_TLB_DATA(r1, r2, imm) \
132 set TTE_LOW_DATA(imm), %r1; \
133 or %r1, %l5, %r1; \
134 mov PAGESIZE_4M, %r2; \
135 sllx %r2, TTE_SIZE_SHIFT, %r2; \
136 or %r1, %r2, %r1; \
137 mov 1, %r2; \
138 sllx %r2, TTE_V_SHIFT, %r2; \
139 or %r1, %r2, %r1;
140
141 ! write DTLB data and install the kernel mapping
142 SET_TLB_DATA(g1, g2, TTE_L | TTE_W) ! use non-global mapping
143 stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
144 membar #Sync
145
146 /*
147 * Because we cannot use global mappings (because we want to
148 * have separate 64-bit address spaces for both the kernel
149 * and the userspace), we prepare the identity mapping also in
150 * context 1. This step is required by the
151 * code installing the ITLB mapping.
152 */
153 ! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)
154 SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
155 stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
156 membar #Sync
157
158 ! write DTLB data and install the kernel mapping in context 1
159 SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping
160 stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
161 membar #Sync
162
163 /*
164 * Now is time to take over the IMMU.
165 * Unfortunatelly, it cannot be done as easily as the DMMU,
166 * because the IMMU is mapping the code it executes.
167 *
168 * [ Note that brave experiments with disabling the IMMU
169 * and using the DMMU approach failed after a dozen
170 * of desparate days with only little success. ]
171 *
172 * The approach used here is inspired from OpenBSD.
173 * First, the kernel creates IMMU mapping for itself
174 * in context 1 (MEM_CONTEXT_TEMP) and switches to
175 * it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
176 * afterwards and replaced with the kernel permanent
177 * mapping. Finally, the kernel switches back to
178 * context 0 and demaps context 1.
179 *
180 * Moreover, the IMMU requires use of the FLUSH instructions.
181 * But that is OK because we always use operands with
182 * addresses already mapped by the taken over DTLB.
183 */
184
185 set kernel_image_start, %g5
186
187 ! write ITLB tag of context 1
188 SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
189 mov VA_DMMU_TAG_ACCESS, %g2
190 stxa %g1, [%g2] ASI_IMMU
191 flush %g5
192
193 ! write ITLB data and install the temporary mapping in context 1
194 SET_TLB_DATA(g1, g2, 0) ! use non-global mapping
195 stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
196 flush %g5
197
198 ! switch to context 1
199 mov MEM_CONTEXT_TEMP, %g1
200 stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
201 flush %g5
202
203 ! demap context 0
204 SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
205 stxa %g0, [%g1] ASI_IMMU_DEMAP
206 flush %g5
207
208 ! write ITLB tag of context 0
209 SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
210 mov VA_DMMU_TAG_ACCESS, %g2
211 stxa %g1, [%g2] ASI_IMMU
212 flush %g5
213
214 ! write ITLB data and install the permanent kernel mapping in context 0
215 SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping
216 stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
217 flush %g5
218
219 ! enter nucleus - using context 0
220 wrpr %g0, 1, %tl
221
222 ! demap context 1
223 SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
224 stxa %g0, [%g1] ASI_IMMU_DEMAP
225 flush %g5
226
227 ! set context 0 in the primary context register
228 stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
229 flush %g5
230
231 ! leave nucleus - using primary context, i.e. context 0
232 wrpr %g0, 0, %tl
233
234 brz %l7, 1f ! skip if you are not the bootstrap CPU
235 nop
236
237 /*
238 * Save physmem_base for use by the mm subsystem.
239 * %l6 contains starting physical address
240 */
241 sethi %hi(physmem_base), %l4
242 stx %l6, [%l4 + %lo(physmem_base)]
243
244 /*
245 * Precompute kernel 8K TLB data template.
246 * %l5 contains starting physical address bits [40:13]
247 */
248 sethi %hi(kernel_8k_tlb_data_template), %l4
249 ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3
250 or %l3, %l5, %l3
251 stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)]
252
253 /*
254 * Flush D-Cache.
255 */
256 call dcache_flush
257 nop
258
259 /*
260 * So far, we have not touched the stack.
261 * It is a good idea to set the kernel stack to a known state now.
262 */
263 sethi %hi(temporary_boot_stack), %sp
264 or %sp, %lo(temporary_boot_stack), %sp
265 sub %sp, STACK_BIAS, %sp
266
267 sethi %hi(bootinfo), %o0
268 call memcpy ! copy bootinfo
269 or %o0, %lo(bootinfo), %o0
270
271 call arch_pre_main
272 nop
273
274 call main_bsp
275 nop
276
277 /* Not reached. */
278
2790:
280 ba 0b
281 nop
282
283
284 /*
285 * Read MID from the processor.
286 */
2871:
288 ldxa [%g0] ASI_UPA_CONFIG, %g1
289 srlx %g1, UPA_CONFIG_MID_SHIFT, %g1
290 and %g1, UPA_CONFIG_MID_MASK, %g1
291
292#ifdef CONFIG_SMP
293 /*
294 * Active loop for APs until the BSP picks them up.
295 * A processor cannot leave the loop until the
296 * global variable 'waking_up_mid' equals its
297 * MID.
298 */
299 set waking_up_mid, %g2
3002:
301 ldx [%g2], %g3
302 cmp %g3, %g1
303 bne 2b
304 nop
305
306 /*
307 * Configure stack for the AP.
308 * The AP is expected to use the stack saved
309 * in the ctx global variable.
310 */
311 set ctx, %g1
312 add %g1, OFFSET_SP, %g1
313 ldx [%g1], %o6
314
315 call main_ap
316 nop
317
318 /* Not reached. */
319#endif
320
3210:
322 ba 0b
323 nop
324
325
326.section K_DATA_START, "aw", @progbits
327
328/*
329 * Create small stack to be used by the bootstrap processor.
330 * It is going to be used only for a very limited period of
331 * time, but we switch to it anyway, just to be sure we are
332 * properly initialized.
333 *
334 * What is important is that this piece of memory is covered
335 * by the 4M DTLB locked entry and therefore there will be
336 * no surprises like deadly combinations of spill trap and
337 * and TLB miss on the stack address.
338 */
339
340#define INITIAL_STACK_SIZE 1024
341
342.align STACK_ALIGNMENT
343 .space INITIAL_STACK_SIZE
344.align STACK_ALIGNMENT
345temporary_boot_stack:
346 .space STACK_WINDOW_SAVE_AREA_SIZE
347
348
349.data
350
351.align 8
352.global physmem_base ! copy of the physical memory base address
353physmem_base:
354 .quad 0
355
356/*
357 * This variable is used by the fast_data_MMU_miss trap handler.
358 * In runtime, it is further modified to reflect the starting address of
359 * physical memory.
360 */
361.global kernel_8k_tlb_data_template
362kernel_8k_tlb_data_template:
363#ifdef CONFIG_VIRT_IDX_DCACHE
364 .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | TTE_CV | TTE_P | TTE_W)
365#else /* CONFIG_VIRT_IDX_DCACHE */
366 .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | TTE_P | TTE_W)
367#endif /* CONFIG_VIRT_IDX_DCACHE */
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