source: mainline/kernel/arch/sparc64/src/sparc64.c@ 233af8c5

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 233af8c5 was a9ac978, checked in by Jakub Jermar <jakub@…>, 19 years ago

SMP stuff for sparc64.
Almost complete except for IPIs.
The absence of IPI support deadlocks
the kernel when more CPUs are configured.

  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup sparc64
30 * @{
31 */
32/** @file
33 */
34
35#include <arch.h>
36#include <debug.h>
37#include <config.h>
38#include <arch/trap/trap.h>
39#include <arch/console.h>
40#include <proc/thread.h>
41#include <console/console.h>
42#include <arch/boot/boot.h>
43#include <arch/arch.h>
44#include <arch/asm.h>
45#include <arch/mm/page.h>
46#include <arch/stack.h>
47#include <genarch/ofw/ofw_tree.h>
48#include <userspace.h>
49
50bootinfo_t bootinfo;
51
52void arch_pre_main(void)
53{
54 /* Copy init task info. */
55 init.cnt = bootinfo.taskmap.count;
56
57 uint32_t i;
58
59 for (i = 0; i < bootinfo.taskmap.count; i++) {
60 init.tasks[i].addr = PA2KA(bootinfo.taskmap.tasks[i].addr);
61 init.tasks[i].size = bootinfo.taskmap.tasks[i].size;
62 }
63
64 /* Copy boot allocations info. */
65 ballocs.base = bootinfo.ballocs.base;
66 ballocs.size = bootinfo.ballocs.size;
67
68 ofw_tree_init(bootinfo.ofw_root);
69}
70
71void arch_pre_mm_init(void)
72{
73 if (config.cpu_active == 1)
74 trap_init();
75}
76
77void arch_post_mm_init(void)
78{
79 if (config.cpu_active == 1)
80 standalone_sparc64_console_init();
81}
82
83void arch_post_cpu_init(void)
84{
85}
86
87void arch_pre_smp_init(void)
88{
89}
90
91void arch_post_smp_init(void)
92{
93 thread_t *t;
94
95 if (config.cpu_active == 1) {
96 /*
97 * Create thread that polls keyboard.
98 */
99 t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll");
100 if (!t)
101 panic("cannot create kkbdpoll\n");
102 thread_ready(t);
103 }
104}
105
106/** Calibrate delay loop.
107 *
108 * On sparc64, we implement delay() by waiting for the TICK register to
109 * reach a pre-computed value, as opposed to performing some pre-computed
110 * amount of instructions of known duration. We set the delay_loop_const
111 * to 1 in order to neutralize the multiplication done by delay().
112 */
113void calibrate_delay_loop(void)
114{
115 CPU->delay_loop_const = 1;
116}
117
118/** Wait several microseconds.
119 *
120 * We assume that interrupts are already disabled.
121 *
122 * @param t Microseconds to wait.
123 */
124void asm_delay_loop(const uint32_t usec)
125{
126 uint64_t stop = tick_read() + (uint64_t) usec * (uint64_t) CPU->arch.clock_frequency / 1000000;
127
128 while (tick_read() < stop)
129 ;
130}
131
132/** Switch to userspace. */
133void userspace(uspace_arg_t *kernel_uarg)
134{
135 switch_to_userspace((uintptr_t) kernel_uarg->uspace_entry,
136 ((uintptr_t) kernel_uarg->uspace_stack) + STACK_SIZE
137 - (ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT) + STACK_BIAS),
138 (uintptr_t) kernel_uarg->uspace_uarg);
139
140 for (;;)
141 ;
142 /* not reached */
143}
144
145/** @}
146 */
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