source: mainline/kernel/arch/sparc64/src/smp/sun4v/smp.c@ 95c4776

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 95c4776 was 95c4776, checked in by Pavel Rimsky <pavel@…>, 15 years ago

Merging SMP (unstable)

  • Property mode set to 100644
File size: 13.9 KB
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1/*
2 * Copyright (c) 2006 Jakub Jermar
3 * Copyright (c) 2009 Pavel Rimsky
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @addtogroup sparc64
31 * @{
32 */
33/** @file
34 */
35
36#include <smp/smp.h>
37#include <smp/ipi.h>
38#include <genarch/ofw/ofw_tree.h>
39#include <cpu.h>
40#include <arch/cpu.h>
41#include <arch/boot/boot.h>
42#include <arch.h>
43#include <config.h>
44#include <macros.h>
45#include <func.h>
46#include <arch/types.h>
47#include <synch/synch.h>
48#include <synch/waitq.h>
49#include <print.h>
50#include <arch/sun4v/hypercall.h>
51#include <arch/sun4v/md.h>
52#include <arch/sun4v/ipi.h>
53#include <time/delay.h>
54#include <arch/smp/sun4v/smp.h>
55#include <string.h>
56
57/** hypervisor code of the "running" state of the CPU */
58#define CPU_STATE_RUNNING 2
59
60/** maximum possible number of processor cores */
61#define MAX_NUM_CORES 8
62
63/** needed in the CPU_START hypercall */
64extern void kernel_image_start(void);
65
66/** needed in the CPU_START hypercall */
67extern void *trap_table;
68
69/** number of execution units detected */
70uint8_t exec_unit_count = 0;
71
72/** execution units (processor cores) */
73exec_unit_t exec_units[MAX_NUM_CORES];
74
75/** CPU structures */
76extern cpu_t *cpus;
77
78/** maximum number of strands per a physical core detected */
79unsigned int max_core_strands = 0;
80
81#ifdef CONFIG_SIMICS_SMP_HACK
82/**
83 * Copies a piece of HelenOS code to the place where OBP had its IPI handler.
84 * By sending an IPI by the BSP to the AP the code will be executed.
85 * The code will jump to the first instruction of the kernel. This is
86 * a workaround how to make APs execute HelenOS code on Simics.
87 */
88static void simics_smp_hack_init(void) {
89 asm volatile (
90 "setx temp_cpu_mondo_handler, %g4, %g6 \n"
91 "setx 0x80200f80, %g4, %g7 \n"
92
93 "ldx [%g6], %g4 \n"
94 "stxa %g4, [%g7] 0x14 \n"
95 "membar #Sync \n"
96
97 "add %g7, 0x8, %g7 \n"
98 "ldx [%g6 + 0x8], %g4 \n"
99 "stxa %g4, [%g7] 0x14 \n"
100 "membar #Sync \n"
101
102 "add %g7, 0x8, %g7 \n"
103 "ldx [%g6 + 0x10], %g4 \n"
104 "stxa %g4, [%g7] 0x14 \n"
105 "membar #Sync \n"
106
107 "add %g7, 0x8, %g7 \n"
108 "ldx [%g6 + 0x18], %g4 \n"
109 "stxa %g4, [%g7] 0x14 \n"
110 "membar #Sync \n"
111
112 "add %g7, 0x8, %g7 \n"
113 "ldx [%g6 + 0x20], %g4 \n"
114 "stxa %g4, [%g7] 0x14 \n"
115 "membar #Sync \n"
116
117 "add %g7, 0x8, %g7 \n"
118 "ldx [%g6 + 0x28], %g4 \n"
119 "stxa %g4, [%g7] 0x14 \n"
120 "membar #Sync \n"
121
122 "add %g7, 0x8, %g7 \n"
123 "ldx [%g6 + 0x30], %g4 \n"
124 "stxa %g4, [%g7] 0x14 \n"
125 "membar #Sync \n"
126
127 "add %g7, 0x8, %g7 \n"
128 "ldx [%g6 + 0x38], %g4 \n"
129 "stxa %g4, [%g7] 0x14 \n"
130 "membar #Sync \n"
131
132 "add %g7, 0x8, %g7 \n"
133 "ldx [%g6 + 0x40], %g4 \n"
134 "stxa %g4, [%g7] 0x14 \n"
135 "membar #Sync \n"
136
137 "flush %i7"
138
139 );
140}
141#endif
142
143#if 0
144/**
145 * Proposes the optimal number of ready threads for each virtual processor
146 * in the given processor core so that the processor core is as busy as the
147 * average processor core. The proposed number of ready threads will be
148 * stored to the proposed_nrdy variable of the cpu_arch_t struture.
149 */
150bool calculate_optimal_nrdy(exec_unit_t *exec_unit) {
151
152 /* calculate the number of threads the core will steal */
153 int avg = atomic_get(&nrdy) / exec_unit_count;
154 int to_steal = avg - atomic_get(&(exec_units->nrdy));
155 if (to_steal < 0) {
156 return true;
157 } else if (to_steal == 0) {
158 return false;
159 }
160
161 /* initialize the proposals with the real numbers of ready threads */
162 unsigned int k;
163 for (k = 0; k < exec_unit->strand_count; k++) {
164 exec_units->cpus[k]->arch.proposed_nrdy =
165 atomic_get(&(exec_unit->cpus[k]->nrdy));
166 }
167
168 /* distribute the threads to be stolen to the core's CPUs */
169 int j;
170 for (j = to_steal; j > 0; j--) {
171 unsigned int k;
172 unsigned int least_busy = 0;
173 unsigned int least_busy_nrdy =
174 exec_unit->cpus[0]->arch.proposed_nrdy;
175
176 /* for each stolen thread, give it to the least busy CPU */
177 for (k = 0; k < exec_unit->strand_count; k++) {
178 if (exec_unit->cpus[k]->arch.proposed_nrdy
179 < least_busy_nrdy) {
180 least_busy = k;
181 least_busy_nrdy =
182 exec_unit->cpus[k]->arch.proposed_nrdy;
183 }
184 }
185 exec_unit->cpus[least_busy]->arch.proposed_nrdy++;
186 }
187
188 return false;
189}
190#endif
191
192/**
193 * Finds out which execution units belong to particular CPUs. By execution unit
194 * we mean the physical core the logical processor is backed by. Since each
195 * Niagara physical core has just one integer execution unit and we will
196 * ignore other execution units than the integer ones, we will use the terms
197 * "integer execution unit", "execution unit" and "physical core"
198 * interchangeably.
199 *
200 * The physical cores are detected by browsing the children of the CPU node
201 * in the machine description and looking for a node representing an integer
202 * execution unit. Once the integer execution unit of a particular CPU is
203 * known, the ID of the CPU is added to the list of cpuids of the corresponding
204 * execution unit structure (exec_unit_t). If an execution unit is encountered
205 * for the first time, a new execution unit structure (exec_unit_t) must be
206 * created first and added to the execution units array (exec_units).
207 *
208 * If the function fails to find an execution unit for a CPU (this may happen
209 * on machines with older firmware or on Simics), it performs a fallback code
210 * which pretends there exists just one execution unit and all CPUs belong to
211 * it.
212 *
213 * Finally, the array of all execution units is reordered such that its element
214 * which represents the physical core of the the bootstrap CPU is at index 0.
215 * Moreover, the array of CPU IDs within the BSP's physical core structure is
216 * reordered such that the element which represents the ID of the BSP is at
217 * index 0. This is done because we would like the CPUs to be woken up
218 * such that the 0-index CPU of the 0-index execution unit is
219 * woken up first. And since the BSP is already woken up, we would like it to be
220 * at 0-th position of the 0-th execution unit structure.
221 *
222 * Apart from that, the code also counts the total number of CPUs and stores
223 * it to the global config.cpu_count variable.
224 */
225static void detect_execution_units(void)
226{
227 /* ID of the bootstrap processor */
228 uint64_t myid;
229
230 /* total number of CPUs detected */
231 size_t cpu_count = 0;
232
233 /* will be set to 1 if detecting the physical cores fails */
234 bool exec_unit_assign_error = 0;
235
236 /* index of the bootstrap physical core in the array of cores */
237 unsigned int bsp_exec_unit_index = 0;
238
239 /* index of the BSP ID inside the array of bootstrap core's cpuids */
240 unsigned int bsp_core_strand_index = 0;
241
242 __hypercall_fast_ret1(0, 0, 0, 0, 0, CPU_MYID, &myid);
243 md_node_t node = md_get_root();
244
245 /* walk through all the CPU nodes in the MD*/
246 while (md_next_node(&node, "cpu")) {
247
248 uint64_t cpuid;
249 md_get_integer_property(node, "id", &cpuid);
250 cpu_count++;
251
252 /*
253 * if failed in previous CPUs, don't try
254 * to detect physical cores any more
255 */
256 if (exec_unit_assign_error)
257 continue;
258
259 /* detect exec. unit for the CPU represented by current node */
260 uint64_t exec_unit_id = 0;
261 md_child_iter_t it = md_get_child_iterator(node);
262
263 while (md_next_child(&it)) {
264 md_node_t child = md_get_child_node(it);
265 const char *exec_unit_type;
266 md_get_string_property(child, "type", &exec_unit_type);
267
268 /* each physical core has just 1 integer exec. unit */
269 if (str_cmp(exec_unit_type, "integer") == 0) {
270 exec_unit_id = child;
271 break;
272 }
273 }
274
275 /* execution unit detected successfully */
276 if (exec_unit_id != 0) {
277
278 /* find the exec. unit in array of existing units */
279 unsigned int i = 0;
280 for (i = 0; i < exec_unit_count; i++) {
281 if (exec_units[i].exec_unit_id == exec_unit_id)
282 break;
283 }
284
285 /*
286 * execution unit just met has not been met before, so
287 * create a new entry in array of all execution units
288 */
289 if (i == exec_unit_count) {
290 exec_units[i].exec_unit_id = exec_unit_id;
291 exec_units[i].strand_count = 0;
292 atomic_set(&(exec_units[i].nrdy), 0);
293 spinlock_initialize(&(exec_units[i].proposed_nrdy_lock), "proposed nrdy lock");
294 exec_unit_count++;
295 }
296
297 /*
298 * remember the exec. unit and strand of the BSP
299 */
300 if (cpuid == myid) {
301 bsp_exec_unit_index = i;
302 bsp_core_strand_index = exec_units[i].strand_count;
303 }
304
305 /* add the CPU just met to the exec. unit's list */
306 exec_units[i].cpuids[exec_units[i].strand_count] = cpuid;
307 exec_units[i].strand_count++;
308 max_core_strands =
309 exec_units[i].strand_count > max_core_strands ?
310 exec_units[i].strand_count : max_core_strands;
311
312 /* detecting execution unit failed */
313 } else {
314 exec_unit_assign_error = 1;
315 }
316 }
317
318 /* save the number of CPUs to a globally accessible variable */
319 config.cpu_count = cpu_count;
320
321 /*
322 * A fallback code which will be executed if finding out which
323 * execution units belong to particular CPUs fails. Pretend there
324 * exists just one execution unit and all CPUs belong to it.
325 */
326 if (exec_unit_assign_error) {
327 bsp_exec_unit_index = 0;
328 exec_unit_count = 1;
329 exec_units[0].strand_count = cpu_count;
330 exec_units[0].exec_unit_id = 1;
331 spinlock_initialize(&(exec_units[0].proposed_nrdy_lock), "proposed nrdy lock");
332 atomic_set(&(exec_units[0].nrdy), 0);
333 max_core_strands = cpu_count;
334
335 /* browse CPUs again, assign them the fictional exec. unit */
336 node = md_get_root();
337 unsigned int i = 0;
338
339 while (md_next_node(&node, "cpu")) {
340 uint64_t cpuid;
341 md_get_integer_property(node, "id", &cpuid);
342 if (cpuid == myid) {
343 bsp_core_strand_index = i;
344 }
345 exec_units[0].cpuids[i++] = cpuid;
346 }
347 }
348
349 /*
350 * Reorder the execution units array elements and the cpuid array
351 * elements so that the BSP will always be the very first CPU of
352 * the very first execution unit.
353 */
354 exec_unit_t temp_exec_unit = exec_units[0];
355 exec_units[0] = exec_units[bsp_exec_unit_index];
356 exec_units[bsp_exec_unit_index] = temp_exec_unit;
357
358 uint64_t temp_cpuid = exec_units[0].cpuids[0];
359 exec_units[0].cpuids[0] = exec_units[0].cpuids[bsp_exec_unit_index];
360 exec_units[0].cpuids[bsp_core_strand_index] = temp_cpuid;
361
362}
363
364/**
365 * Determine number of processors and detect physical cores. On Simics
366 * copy the code which will be executed by the AP when the BSP sends an
367 * IPI to it in order to make it execute HelenOS code.
368 */
369void smp_init(void)
370{
371 detect_execution_units();
372#ifdef CONFIG_SIMICS_SMP_HACK
373 simics_smp_hack_init();
374#endif
375}
376
377/**
378 * For each CPU sets the value of cpus[i].arch.id, where i is the
379 * index of the CPU in the cpus variable, to the cpuid of the i-th processor
380 * to be run. The CPUs are run such that the CPU represented by cpus[0]
381 * is run first, cpus[1] is run after it, and cpus[cpu_count - 1] is run as the
382 * last one.
383 *
384 * The CPU IDs are set such that during waking the CPUs up the
385 * processor cores will be alternated, i.e. first one CPU from the first core
386 * will be run, after that one CPU from the second CPU core will be run,...
387 * then one CPU from the last core will be run, after that another CPU
388 * from the first core will be run, then another CPU from the second core
389 * will be run,... then another CPU from the last core will be run, and so on.
390 */
391static void init_cpuids(void)
392{
393 unsigned int cur_core_strand;
394 unsigned int cur_core;
395 unsigned int cur_cpu = 0;
396
397 for (cur_core_strand = 0; cur_core_strand < max_core_strands; cur_core_strand++) {
398 for (cur_core = 0; cur_core < exec_unit_count; cur_core++) {
399 if (cur_core_strand > exec_units[cur_core].strand_count)
400 continue;
401
402 cpus[cur_cpu].arch.exec_unit = &(exec_units[cur_core]);
403 atomic_add(&(exec_units[cur_core].nrdy), atomic_get(&(cpus[cur_cpu].nrdy)));
404 cpus[cur_cpu].arch.id = exec_units[cur_core].cpuids[cur_core_strand];
405 exec_units[cur_core].cpus[cur_core_strand] = &(cpus[cur_cpu]);
406 cur_cpu++;
407 }
408 }
409}
410
411/**
412 * Wakes up a single CPU.
413 *
414 * @param cpuid ID of the CPU to be woken up
415 */
416static bool wake_cpu(uint64_t cpuid)
417{
418
419#ifdef CONFIG_SIMICS_SMP_HACK
420 ipi_unicast_to((void (*)(void)) 1234, cpuid);
421#else
422 /* stop the CPU before making it execute our code */
423 if (__hypercall_fast1(CPU_STOP, cpuid) != EOK)
424 return false;
425
426 /* wait for the CPU to stop */
427 uint64_t state;
428 __hypercall_fast_ret1(cpuid, 0, 0, 0, 0,
429 CPU_STATE, &state);
430 while (state == CPU_STATE_RUNNING) {
431 __hypercall_fast_ret1(cpuid, 0, 0, 0, 0,
432 CPU_STATE, &state);
433 }
434
435 /* make the CPU run again and execute HelenOS code */
436 if (__hypercall_fast4(
437 CPU_START, cpuid,
438 (uint64_t) KA2PA(kernel_image_start),
439 KA2PA(trap_table), bootinfo.physmem_start
440 ) != EOK)
441 return false;
442#endif
443
444 if (waitq_sleep_timeout(&ap_completion_wq, 10000000, SYNCH_FLAGS_NONE) ==
445 ESYNCH_TIMEOUT)
446 printf("%s: waiting for processor (cpuid = %" PRIu32
447 ") timed out\n", __func__, cpuid);
448
449 return true;
450}
451
452/** Wake application processors up. */
453void kmp(void *arg)
454{
455 init_cpuids();
456
457 unsigned int i;
458
459 for (i = 1; i < config.cpu_count; i++) {
460 wake_cpu(cpus[i].arch.id);
461 }
462}
463
464/** @}
465 */
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