1 | /*
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2 | * Copyright (C) 2005 Jakub Jermar
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3 | * All rights reserved.
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4 | *
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5 | * Redistribution and use in source and binary forms, with or without
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6 | * modification, are permitted provided that the following conditions
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7 | * are met:
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8 | *
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9 | * - Redistributions of source code must retain the above copyright
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10 | * notice, this list of conditions and the following disclaimer.
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11 | * - Redistributions in binary form must reproduce the above copyright
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12 | * notice, this list of conditions and the following disclaimer in the
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13 | * documentation and/or other materials provided with the distribution.
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14 | * - The name of the author may not be used to endorse or promote products
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15 | * derived from this software without specific prior written permission.
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16 | *
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 | */
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28 |
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29 | /** @addtogroup sparc64mm
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30 | * @{
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31 | */
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32 | /** @file
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33 | */
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34 |
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35 | #include <arch/mm/tlb.h>
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36 | #include <mm/tlb.h>
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37 | #include <mm/as.h>
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38 | #include <mm/asid.h>
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39 | #include <arch/mm/frame.h>
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40 | #include <arch/mm/page.h>
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41 | #include <arch/mm/mmu.h>
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42 | #include <arch/interrupt.h>
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43 | #include <interrupt.h>
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44 | #include <arch.h>
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45 | #include <print.h>
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46 | #include <arch/types.h>
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47 | #include <typedefs.h>
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48 | #include <config.h>
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49 | #include <arch/trap/trap.h>
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50 | #include <arch/trap/exception.h>
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51 | #include <panic.h>
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52 | #include <arch/asm.h>
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53 |
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54 | #ifdef CONFIG_TSB
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55 | #include <arch/mm/tsb.h>
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56 | #endif
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57 |
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58 | static void dtlb_pte_copy(pte_t *t, bool ro);
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59 | static void itlb_pte_copy(pte_t *t);
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60 | static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str);
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61 | static void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str);
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62 | static void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str);
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63 |
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64 | char *context_encoding[] = {
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65 | "Primary",
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66 | "Secondary",
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67 | "Nucleus",
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68 | "Reserved"
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69 | };
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70 |
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71 | void tlb_arch_init(void)
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72 | {
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73 | /*
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74 | * Invalidate all non-locked DTLB and ITLB entries.
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75 | */
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76 | tlb_invalidate_all();
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77 |
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78 | /*
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79 | * Clear both SFSRs.
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80 | */
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81 | dtlb_sfsr_write(0);
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82 | itlb_sfsr_write(0);
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83 | }
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84 |
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85 | /** Insert privileged mapping into DMMU TLB.
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86 | *
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87 | * @param page Virtual page address.
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88 | * @param frame Physical frame address.
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89 | * @param pagesize Page size.
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90 | * @param locked True for permanent mappings, false otherwise.
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91 | * @param cacheable True if the mapping is cacheable, false otherwise.
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92 | */
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93 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
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94 | {
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95 | tlb_tag_access_reg_t tag;
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96 | tlb_data_t data;
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97 | page_address_t pg;
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98 | frame_address_t fr;
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99 |
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100 | pg.address = page;
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101 | fr.address = frame;
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102 |
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103 | tag.value = ASID_KERNEL;
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104 | tag.vpn = pg.vpn;
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105 |
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106 | dtlb_tag_access_write(tag.value);
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107 |
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108 | data.value = 0;
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109 | data.v = true;
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110 | data.size = pagesize;
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111 | data.pfn = fr.pfn;
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112 | data.l = locked;
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113 | data.cp = cacheable;
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114 | data.cv = cacheable;
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115 | data.p = true;
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116 | data.w = true;
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117 | data.g = false;
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118 |
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119 | dtlb_data_in_write(data.value);
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120 | }
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121 |
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122 | /** Copy PTE to TLB.
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123 | *
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124 | * @param t Page Table Entry to be copied.
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125 | * @param ro If true, the entry will be created read-only, regardless of its w field.
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126 | */
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127 | void dtlb_pte_copy(pte_t *t, bool ro)
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128 | {
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129 | tlb_tag_access_reg_t tag;
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130 | tlb_data_t data;
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131 | page_address_t pg;
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132 | frame_address_t fr;
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133 |
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134 | pg.address = t->page;
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135 | fr.address = t->frame;
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136 |
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137 | tag.value = 0;
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138 | tag.context = t->as->asid;
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139 | tag.vpn = pg.vpn;
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140 |
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141 | dtlb_tag_access_write(tag.value);
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142 |
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143 | data.value = 0;
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144 | data.v = true;
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145 | data.size = PAGESIZE_8K;
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146 | data.pfn = fr.pfn;
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147 | data.l = false;
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148 | data.cp = t->c;
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149 | data.cv = t->c;
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150 | data.p = t->k; /* p like privileged */
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151 | data.w = ro ? false : t->w;
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152 | data.g = t->g;
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153 |
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154 | dtlb_data_in_write(data.value);
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155 | }
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156 |
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157 | /** Copy PTE to ITLB.
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158 | *
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159 | * @param t Page Table Entry to be copied.
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160 | */
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161 | void itlb_pte_copy(pte_t *t)
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162 | {
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163 | tlb_tag_access_reg_t tag;
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164 | tlb_data_t data;
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165 | page_address_t pg;
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166 | frame_address_t fr;
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167 |
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168 | pg.address = t->page;
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169 | fr.address = t->frame;
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170 |
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171 | tag.value = 0;
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172 | tag.context = t->as->asid;
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173 | tag.vpn = pg.vpn;
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174 |
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175 | itlb_tag_access_write(tag.value);
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176 |
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177 | data.value = 0;
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178 | data.v = true;
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179 | data.size = PAGESIZE_8K;
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180 | data.pfn = fr.pfn;
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181 | data.l = false;
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182 | data.cp = t->c;
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183 | data.cv = t->c;
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184 | data.p = t->k; /* p like privileged */
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185 | data.w = false;
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186 | data.g = t->g;
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187 |
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188 | itlb_data_in_write(data.value);
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189 | }
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190 |
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191 | /** ITLB miss handler. */
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192 | void fast_instruction_access_mmu_miss(int n, istate_t *istate)
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193 | {
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194 | uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
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195 | pte_t *t;
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196 |
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197 | page_table_lock(AS, true);
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198 | t = page_mapping_find(AS, va);
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199 | if (t && PTE_EXECUTABLE(t)) {
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200 | /*
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201 | * The mapping was found in the software page hash table.
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202 | * Insert it into ITLB.
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203 | */
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204 | t->a = true;
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205 | itlb_pte_copy(t);
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206 | #ifdef CONFIG_TSB
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207 | itsb_pte_copy(t);
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208 | #endif
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209 | page_table_unlock(AS, true);
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210 | } else {
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211 | /*
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212 | * Forward the page fault to the address space page fault handler.
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213 | */
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214 | page_table_unlock(AS, true);
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215 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
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216 | do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__);
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217 | }
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218 | }
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219 | }
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220 |
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221 | /** DTLB miss handler.
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222 | *
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223 | * Note that some faults (e.g. kernel faults) were already resolved
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224 | * by the low-level, assembly language part of the fast_data_access_mmu_miss
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225 | * handler.
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226 | */
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227 | void fast_data_access_mmu_miss(int n, istate_t *istate)
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228 | {
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229 | tlb_tag_access_reg_t tag;
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230 | uintptr_t va;
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231 | pte_t *t;
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232 |
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233 | tag.value = dtlb_tag_access_read();
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234 | va = tag.vpn << PAGE_WIDTH;
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235 |
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236 | if (tag.context == ASID_KERNEL) {
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237 | if (!tag.vpn) {
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238 | /* NULL access in kernel */
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239 | do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
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240 | }
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241 | do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault.");
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242 | }
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243 |
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244 | page_table_lock(AS, true);
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245 | t = page_mapping_find(AS, va);
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246 | if (t) {
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247 | /*
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248 | * The mapping was found in the software page hash table.
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249 | * Insert it into DTLB.
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250 | */
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251 | t->a = true;
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252 | dtlb_pte_copy(t, true);
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253 | #ifdef CONFIG_TSB
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254 | dtsb_pte_copy(t, true);
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255 | #endif
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256 | page_table_unlock(AS, true);
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257 | } else {
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258 | /*
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259 | * Forward the page fault to the address space page fault handler.
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260 | */
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261 | page_table_unlock(AS, true);
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262 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
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263 | do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
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264 | }
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265 | }
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266 | }
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267 |
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268 | /** DTLB protection fault handler. */
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269 | void fast_data_access_protection(int n, istate_t *istate)
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270 | {
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271 | tlb_tag_access_reg_t tag;
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272 | uintptr_t va;
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273 | pte_t *t;
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274 |
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275 | tag.value = dtlb_tag_access_read();
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276 | va = tag.vpn << PAGE_WIDTH;
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277 |
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278 | page_table_lock(AS, true);
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279 | t = page_mapping_find(AS, va);
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280 | if (t && PTE_WRITABLE(t)) {
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281 | /*
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282 | * The mapping was found in the software page hash table and is writable.
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283 | * Demap the old mapping and insert an updated mapping into DTLB.
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284 | */
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285 | t->a = true;
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286 | t->d = true;
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287 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);
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288 | dtlb_pte_copy(t, false);
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289 | #ifdef CONFIG_TSB
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290 | dtsb_pte_copy(t, false);
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291 | #endif
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292 | page_table_unlock(AS, true);
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293 | } else {
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294 | /*
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295 | * Forward the page fault to the address space page fault handler.
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296 | */
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297 | page_table_unlock(AS, true);
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298 | if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
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299 | do_fast_data_access_protection_fault(istate, tag, __FUNCTION__);
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300 | }
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301 | }
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302 | }
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303 |
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304 | /** Print contents of both TLBs. */
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305 | void tlb_print(void)
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306 | {
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307 | int i;
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308 | tlb_data_t d;
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309 | tlb_tag_read_reg_t t;
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310 |
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311 | printf("I-TLB contents:\n");
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312 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
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313 | d.value = itlb_data_access_read(i);
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314 | t.value = itlb_tag_read_read(i);
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315 |
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316 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
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317 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
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318 | }
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319 |
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320 | printf("D-TLB contents:\n");
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321 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
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322 | d.value = dtlb_data_access_read(i);
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323 | t.value = dtlb_tag_read_read(i);
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324 |
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325 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
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326 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
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327 | }
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328 |
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329 | }
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330 |
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331 | void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str)
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332 | {
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333 | fault_if_from_uspace(istate, "%s\n", str);
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334 | dump_istate(istate);
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335 | panic("%s\n", str);
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336 | }
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337 |
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338 | void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str)
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339 | {
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340 | uintptr_t va;
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341 |
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342 | va = tag.vpn << PAGE_WIDTH;
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343 |
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344 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
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345 | dump_istate(istate);
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346 | printf("Faulting page: %p, ASID=%d\n", va, tag.context);
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347 | panic("%s\n", str);
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348 | }
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349 |
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350 | void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str)
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351 | {
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352 | uintptr_t va;
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353 |
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354 | va = tag.vpn << PAGE_WIDTH;
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355 |
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356 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
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357 | printf("Faulting page: %p, ASID=%d\n", va, tag.context);
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358 | dump_istate(istate);
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359 | panic("%s\n", str);
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360 | }
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361 |
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362 | void dump_sfsr_and_sfar(void)
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363 | {
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364 | tlb_sfsr_reg_t sfsr;
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365 | uintptr_t sfar;
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366 |
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367 | sfsr.value = dtlb_sfsr_read();
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368 | sfar = dtlb_sfar_read();
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369 |
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370 | printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, fv=%d\n",
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371 | sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
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372 | printf("DTLB SFAR: address=%p\n", sfar);
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373 |
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374 | dtlb_sfsr_write(0);
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375 | }
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376 |
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377 | /** Invalidate all unlocked ITLB and DTLB entries. */
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378 | void tlb_invalidate_all(void)
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379 | {
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380 | int i;
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381 | tlb_data_t d;
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382 | tlb_tag_read_reg_t t;
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383 |
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384 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
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385 | d.value = itlb_data_access_read(i);
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386 | if (!d.l) {
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387 | t.value = itlb_tag_read_read(i);
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388 | d.v = false;
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389 | itlb_tag_access_write(t.value);
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390 | itlb_data_access_write(i, d.value);
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391 | }
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392 | }
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393 |
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394 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
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395 | d.value = dtlb_data_access_read(i);
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396 | if (!d.l) {
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397 | t.value = dtlb_tag_read_read(i);
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398 | d.v = false;
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399 | dtlb_tag_access_write(t.value);
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400 | dtlb_data_access_write(i, d.value);
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401 | }
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402 | }
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403 |
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404 | }
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405 |
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406 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
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407 | *
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408 | * @param asid Address Space ID.
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409 | */
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410 | void tlb_invalidate_asid(asid_t asid)
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411 | {
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412 | tlb_context_reg_t pc_save, ctx;
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413 |
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414 | /* switch to nucleus because we are mapped by the primary context */
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415 | nucleus_enter();
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416 |
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417 | ctx.v = pc_save.v = mmu_primary_context_read();
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418 | ctx.context = asid;
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419 | mmu_primary_context_write(ctx.v);
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420 |
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421 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
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422 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
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423 |
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424 | mmu_primary_context_write(pc_save.v);
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425 |
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426 | nucleus_leave();
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427 | }
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428 |
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429 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
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430 | *
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431 | * @param asid Address Space ID.
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432 | * @param page First page which to sweep out from ITLB and DTLB.
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433 | * @param cnt Number of ITLB and DTLB entries to invalidate.
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434 | */
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435 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
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436 | {
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437 | int i;
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438 | tlb_context_reg_t pc_save, ctx;
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439 |
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440 | /* switch to nucleus because we are mapped by the primary context */
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441 | nucleus_enter();
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442 |
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443 | ctx.v = pc_save.v = mmu_primary_context_read();
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444 | ctx.context = asid;
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445 | mmu_primary_context_write(ctx.v);
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446 |
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447 | for (i = 0; i < cnt; i++) {
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448 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
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449 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
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450 | }
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451 |
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452 | mmu_primary_context_write(pc_save.v);
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453 |
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454 | nucleus_leave();
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455 | }
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456 |
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457 | /** @}
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458 | */
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