source: mainline/kernel/arch/sparc64/src/mm/tlb.c@ 3869e9c5

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3869e9c5 was 8cee705, checked in by Jakub Jermar <jakub@…>, 19 years ago

sparc64 work.

  • Improve panic screen on data_access_exception by dumping contents of DSFSR and DSFAR.
  • Change the FHC enable interrupt code to only set the IMAP_V bit.
  • Property mode set to 100644
File size: 11.4 KB
Line 
1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup sparc64mm
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/mm/tlb.h>
36#include <mm/tlb.h>
37#include <mm/as.h>
38#include <mm/asid.h>
39#include <arch/mm/frame.h>
40#include <arch/mm/page.h>
41#include <arch/mm/mmu.h>
42#include <arch/interrupt.h>
43#include <interrupt.h>
44#include <arch.h>
45#include <print.h>
46#include <arch/types.h>
47#include <typedefs.h>
48#include <config.h>
49#include <arch/trap/trap.h>
50#include <arch/trap/exception.h>
51#include <panic.h>
52#include <arch/asm.h>
53
54#ifdef CONFIG_TSB
55#include <arch/mm/tsb.h>
56#endif
57
58static void dtlb_pte_copy(pte_t *t, bool ro);
59static void itlb_pte_copy(pte_t *t);
60static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str);
61static void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str);
62static void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str);
63
64char *context_encoding[] = {
65 "Primary",
66 "Secondary",
67 "Nucleus",
68 "Reserved"
69};
70
71void tlb_arch_init(void)
72{
73 /*
74 * Invalidate all non-locked DTLB and ITLB entries.
75 */
76 tlb_invalidate_all();
77
78 /*
79 * Clear both SFSRs.
80 */
81 dtlb_sfsr_write(0);
82 itlb_sfsr_write(0);
83}
84
85/** Insert privileged mapping into DMMU TLB.
86 *
87 * @param page Virtual page address.
88 * @param frame Physical frame address.
89 * @param pagesize Page size.
90 * @param locked True for permanent mappings, false otherwise.
91 * @param cacheable True if the mapping is cacheable, false otherwise.
92 */
93void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
94{
95 tlb_tag_access_reg_t tag;
96 tlb_data_t data;
97 page_address_t pg;
98 frame_address_t fr;
99
100 pg.address = page;
101 fr.address = frame;
102
103 tag.value = ASID_KERNEL;
104 tag.vpn = pg.vpn;
105
106 dtlb_tag_access_write(tag.value);
107
108 data.value = 0;
109 data.v = true;
110 data.size = pagesize;
111 data.pfn = fr.pfn;
112 data.l = locked;
113 data.cp = cacheable;
114 data.cv = cacheable;
115 data.p = true;
116 data.w = true;
117 data.g = false;
118
119 dtlb_data_in_write(data.value);
120}
121
122/** Copy PTE to TLB.
123 *
124 * @param t Page Table Entry to be copied.
125 * @param ro If true, the entry will be created read-only, regardless of its w field.
126 */
127void dtlb_pte_copy(pte_t *t, bool ro)
128{
129 tlb_tag_access_reg_t tag;
130 tlb_data_t data;
131 page_address_t pg;
132 frame_address_t fr;
133
134 pg.address = t->page;
135 fr.address = t->frame;
136
137 tag.value = 0;
138 tag.context = t->as->asid;
139 tag.vpn = pg.vpn;
140
141 dtlb_tag_access_write(tag.value);
142
143 data.value = 0;
144 data.v = true;
145 data.size = PAGESIZE_8K;
146 data.pfn = fr.pfn;
147 data.l = false;
148 data.cp = t->c;
149 data.cv = t->c;
150 data.p = t->k; /* p like privileged */
151 data.w = ro ? false : t->w;
152 data.g = t->g;
153
154 dtlb_data_in_write(data.value);
155}
156
157/** Copy PTE to ITLB.
158 *
159 * @param t Page Table Entry to be copied.
160 */
161void itlb_pte_copy(pte_t *t)
162{
163 tlb_tag_access_reg_t tag;
164 tlb_data_t data;
165 page_address_t pg;
166 frame_address_t fr;
167
168 pg.address = t->page;
169 fr.address = t->frame;
170
171 tag.value = 0;
172 tag.context = t->as->asid;
173 tag.vpn = pg.vpn;
174
175 itlb_tag_access_write(tag.value);
176
177 data.value = 0;
178 data.v = true;
179 data.size = PAGESIZE_8K;
180 data.pfn = fr.pfn;
181 data.l = false;
182 data.cp = t->c;
183 data.cv = t->c;
184 data.p = t->k; /* p like privileged */
185 data.w = false;
186 data.g = t->g;
187
188 itlb_data_in_write(data.value);
189}
190
191/** ITLB miss handler. */
192void fast_instruction_access_mmu_miss(int n, istate_t *istate)
193{
194 uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
195 pte_t *t;
196
197 page_table_lock(AS, true);
198 t = page_mapping_find(AS, va);
199 if (t && PTE_EXECUTABLE(t)) {
200 /*
201 * The mapping was found in the software page hash table.
202 * Insert it into ITLB.
203 */
204 t->a = true;
205 itlb_pte_copy(t);
206#ifdef CONFIG_TSB
207 itsb_pte_copy(t);
208#endif
209 page_table_unlock(AS, true);
210 } else {
211 /*
212 * Forward the page fault to the address space page fault handler.
213 */
214 page_table_unlock(AS, true);
215 if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
216 do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__);
217 }
218 }
219}
220
221/** DTLB miss handler.
222 *
223 * Note that some faults (e.g. kernel faults) were already resolved
224 * by the low-level, assembly language part of the fast_data_access_mmu_miss
225 * handler.
226 */
227void fast_data_access_mmu_miss(int n, istate_t *istate)
228{
229 tlb_tag_access_reg_t tag;
230 uintptr_t va;
231 pte_t *t;
232
233 tag.value = dtlb_tag_access_read();
234 va = tag.vpn << PAGE_WIDTH;
235
236 if (tag.context == ASID_KERNEL) {
237 if (!tag.vpn) {
238 /* NULL access in kernel */
239 do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
240 }
241 do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault.");
242 }
243
244 page_table_lock(AS, true);
245 t = page_mapping_find(AS, va);
246 if (t) {
247 /*
248 * The mapping was found in the software page hash table.
249 * Insert it into DTLB.
250 */
251 t->a = true;
252 dtlb_pte_copy(t, true);
253#ifdef CONFIG_TSB
254 dtsb_pte_copy(t, true);
255#endif
256 page_table_unlock(AS, true);
257 } else {
258 /*
259 * Forward the page fault to the address space page fault handler.
260 */
261 page_table_unlock(AS, true);
262 if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
263 do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
264 }
265 }
266}
267
268/** DTLB protection fault handler. */
269void fast_data_access_protection(int n, istate_t *istate)
270{
271 tlb_tag_access_reg_t tag;
272 uintptr_t va;
273 pte_t *t;
274
275 tag.value = dtlb_tag_access_read();
276 va = tag.vpn << PAGE_WIDTH;
277
278 page_table_lock(AS, true);
279 t = page_mapping_find(AS, va);
280 if (t && PTE_WRITABLE(t)) {
281 /*
282 * The mapping was found in the software page hash table and is writable.
283 * Demap the old mapping and insert an updated mapping into DTLB.
284 */
285 t->a = true;
286 t->d = true;
287 dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);
288 dtlb_pte_copy(t, false);
289#ifdef CONFIG_TSB
290 dtsb_pte_copy(t, false);
291#endif
292 page_table_unlock(AS, true);
293 } else {
294 /*
295 * Forward the page fault to the address space page fault handler.
296 */
297 page_table_unlock(AS, true);
298 if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
299 do_fast_data_access_protection_fault(istate, tag, __FUNCTION__);
300 }
301 }
302}
303
304/** Print contents of both TLBs. */
305void tlb_print(void)
306{
307 int i;
308 tlb_data_t d;
309 tlb_tag_read_reg_t t;
310
311 printf("I-TLB contents:\n");
312 for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
313 d.value = itlb_data_access_read(i);
314 t.value = itlb_tag_read_read(i);
315
316 printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
317 i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
318 }
319
320 printf("D-TLB contents:\n");
321 for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
322 d.value = dtlb_data_access_read(i);
323 t.value = dtlb_tag_read_read(i);
324
325 printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
326 i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
327 }
328
329}
330
331void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str)
332{
333 fault_if_from_uspace(istate, "%s\n", str);
334 dump_istate(istate);
335 panic("%s\n", str);
336}
337
338void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str)
339{
340 uintptr_t va;
341
342 va = tag.vpn << PAGE_WIDTH;
343
344 fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
345 dump_istate(istate);
346 printf("Faulting page: %p, ASID=%d\n", va, tag.context);
347 panic("%s\n", str);
348}
349
350void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str)
351{
352 uintptr_t va;
353
354 va = tag.vpn << PAGE_WIDTH;
355
356 fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
357 printf("Faulting page: %p, ASID=%d\n", va, tag.context);
358 dump_istate(istate);
359 panic("%s\n", str);
360}
361
362void dump_sfsr_and_sfar(void)
363{
364 tlb_sfsr_reg_t sfsr;
365 uintptr_t sfar;
366
367 sfsr.value = dtlb_sfsr_read();
368 sfar = dtlb_sfar_read();
369
370 printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, fv=%d\n",
371 sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
372 printf("DTLB SFAR: address=%p\n", sfar);
373
374 dtlb_sfsr_write(0);
375}
376
377/** Invalidate all unlocked ITLB and DTLB entries. */
378void tlb_invalidate_all(void)
379{
380 int i;
381 tlb_data_t d;
382 tlb_tag_read_reg_t t;
383
384 for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
385 d.value = itlb_data_access_read(i);
386 if (!d.l) {
387 t.value = itlb_tag_read_read(i);
388 d.v = false;
389 itlb_tag_access_write(t.value);
390 itlb_data_access_write(i, d.value);
391 }
392 }
393
394 for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
395 d.value = dtlb_data_access_read(i);
396 if (!d.l) {
397 t.value = dtlb_tag_read_read(i);
398 d.v = false;
399 dtlb_tag_access_write(t.value);
400 dtlb_data_access_write(i, d.value);
401 }
402 }
403
404}
405
406/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
407 *
408 * @param asid Address Space ID.
409 */
410void tlb_invalidate_asid(asid_t asid)
411{
412 tlb_context_reg_t pc_save, ctx;
413
414 /* switch to nucleus because we are mapped by the primary context */
415 nucleus_enter();
416
417 ctx.v = pc_save.v = mmu_primary_context_read();
418 ctx.context = asid;
419 mmu_primary_context_write(ctx.v);
420
421 itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
422 dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
423
424 mmu_primary_context_write(pc_save.v);
425
426 nucleus_leave();
427}
428
429/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
430 *
431 * @param asid Address Space ID.
432 * @param page First page which to sweep out from ITLB and DTLB.
433 * @param cnt Number of ITLB and DTLB entries to invalidate.
434 */
435void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
436{
437 int i;
438 tlb_context_reg_t pc_save, ctx;
439
440 /* switch to nucleus because we are mapped by the primary context */
441 nucleus_enter();
442
443 ctx.v = pc_save.v = mmu_primary_context_read();
444 ctx.context = asid;
445 mmu_primary_context_write(ctx.v);
446
447 for (i = 0; i < cnt; i++) {
448 itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
449 dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
450 }
451
452 mmu_primary_context_write(pc_save.v);
453
454 nucleus_leave();
455}
456
457/** @}
458 */
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