[0d04024] | 1 | /*
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| 2 | * Copyright (C) 2005 Jakub Jermar
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[10b890b] | 29 | /** @addtogroup sparc64mm
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[0d04024] | 35 | #include <arch/mm/tlb.h>
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| 36 | #include <mm/tlb.h>
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[0cfc4d38] | 37 | #include <arch/mm/frame.h>
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| 38 | #include <arch/mm/page.h>
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| 39 | #include <arch/mm/mmu.h>
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[68656282] | 40 | #include <mm/asid.h>
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[0d04024] | 41 | #include <print.h>
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[dbb6886] | 42 | #include <arch/types.h>
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| 43 | #include <typedefs.h>
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[0cfc4d38] | 44 | #include <config.h>
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[49b6d32] | 45 | #include <arch/trap/trap.h>
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[008029d] | 46 | #include <panic.h>
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[b6fba84] | 47 | #include <arch/asm.h>
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| 48 | #include <symtab.h>
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[02f441c0] | 49 |
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[7cb53f62] | 50 | #include <arch/drivers/fb.h>
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[30ab05f] | 51 | #include <arch/drivers/i8042.h>
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[b6fba84] | 52 |
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| 53 | char *context_encoding[] = {
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| 54 | "Primary",
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| 55 | "Secondary",
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| 56 | "Nucleus",
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| 57 | "Reserved"
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| 58 | };
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[0d04024] | 59 |
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| 60 | void tlb_arch_init(void)
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| 61 | {
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[97f1691] | 62 | }
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[b6fba84] | 63 |
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[97f1691] | 64 | /** Insert privileged mapping into DMMU TLB.
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| 65 | *
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| 66 | * @param page Virtual page address.
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| 67 | * @param frame Physical frame address.
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| 68 | * @param pagesize Page size.
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| 69 | * @param locked True for permanent mappings, false otherwise.
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| 70 | * @param cacheable True if the mapping is cacheable, false otherwise.
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| 71 | */
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[7f1c620] | 72 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
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[97f1691] | 73 | {
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| 74 | tlb_tag_access_reg_t tag;
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| 75 | tlb_data_t data;
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| 76 | page_address_t pg;
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| 77 | frame_address_t fr;
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[b6fba84] | 78 |
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[97f1691] | 79 | pg.address = page;
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| 80 | fr.address = frame;
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[02f441c0] | 81 |
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| 82 | tag.value = ASID_KERNEL;
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| 83 | tag.vpn = pg.vpn;
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| 84 |
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| 85 | dtlb_tag_access_write(tag.value);
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| 86 |
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| 87 | data.value = 0;
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| 88 | data.v = true;
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[97f1691] | 89 | data.size = pagesize;
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[02f441c0] | 90 | data.pfn = fr.pfn;
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[97f1691] | 91 | data.l = locked;
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| 92 | data.cp = cacheable;
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| 93 | data.cv = cacheable;
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[02f441c0] | 94 | data.p = true;
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| 95 | data.w = true;
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| 96 | data.g = true;
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| 97 |
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| 98 | dtlb_data_in_write(data.value);
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[0d04024] | 99 | }
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| 100 |
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[008029d] | 101 | /** ITLB miss handler. */
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| 102 | void fast_instruction_access_mmu_miss(void)
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| 103 | {
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| 104 | panic("%s\n", __FUNCTION__);
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| 105 | }
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| 106 |
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| 107 | /** DTLB miss handler. */
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| 108 | void fast_data_access_mmu_miss(void)
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| 109 | {
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[68656282] | 110 | tlb_tag_access_reg_t tag;
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[7f1c620] | 111 | uintptr_t tpc;
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[b6fba84] | 112 | char *tpc_str;
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[7cb53f62] | 113 |
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[68656282] | 114 | tag.value = dtlb_tag_access_read();
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| 115 | if (tag.context != ASID_KERNEL || tag.vpn == 0) {
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| 116 | tpc = tpc_read();
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| 117 | tpc_str = get_symtab_entry(tpc);
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| 118 |
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[cf85e24c] | 119 | printf("Faulting page: %p, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
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| 120 | printf("TPC=%p, (%s)\n", tpc, tpc_str ? tpc_str : "?");
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[68656282] | 121 | panic("%s\n", __FUNCTION__);
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| 122 | }
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| 123 |
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| 124 | /*
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| 125 | * Identity map piece of faulting kernel address space.
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| 126 | */
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[97f1691] | 127 | dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);
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[008029d] | 128 | }
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| 129 |
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| 130 | /** DTLB protection fault handler. */
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| 131 | void fast_data_access_protection(void)
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| 132 | {
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| 133 | panic("%s\n", __FUNCTION__);
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| 134 | }
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| 135 |
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[0d04024] | 136 | /** Print contents of both TLBs. */
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| 137 | void tlb_print(void)
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| 138 | {
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| 139 | int i;
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| 140 | tlb_data_t d;
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| 141 | tlb_tag_read_reg_t t;
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| 142 |
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| 143 | printf("I-TLB contents:\n");
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| 144 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
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| 145 | d.value = itlb_data_access_read(i);
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[c52ed6b] | 146 | t.value = itlb_tag_read_read(i);
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[0d04024] | 147 |
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[fbf7b4c] | 148 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
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[dbb6886] | 149 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
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[0d04024] | 150 | }
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| 151 |
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| 152 | printf("D-TLB contents:\n");
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| 153 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
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| 154 | d.value = dtlb_data_access_read(i);
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[c52ed6b] | 155 | t.value = dtlb_tag_read_read(i);
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[0d04024] | 156 |
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[fbf7b4c] | 157 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
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[dbb6886] | 158 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
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[0d04024] | 159 | }
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| 160 |
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| 161 | }
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[dbb6886] | 162 |
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| 163 | /** Invalidate all unlocked ITLB and DTLB entries. */
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| 164 | void tlb_invalidate_all(void)
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| 165 | {
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| 166 | int i;
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| 167 | tlb_data_t d;
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| 168 | tlb_tag_read_reg_t t;
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| 169 |
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| 170 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
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| 171 | d.value = itlb_data_access_read(i);
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| 172 | if (!d.l) {
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| 173 | t.value = itlb_tag_read_read(i);
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| 174 | d.v = false;
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| 175 | itlb_tag_access_write(t.value);
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| 176 | itlb_data_access_write(i, d.value);
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| 177 | }
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| 178 | }
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| 179 |
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| 180 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
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| 181 | d.value = dtlb_data_access_read(i);
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| 182 | if (!d.l) {
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| 183 | t.value = dtlb_tag_read_read(i);
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| 184 | d.v = false;
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| 185 | dtlb_tag_access_write(t.value);
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| 186 | dtlb_data_access_write(i, d.value);
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| 187 | }
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| 188 | }
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| 189 |
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| 190 | }
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| 191 |
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| 192 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
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| 193 | *
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| 194 | * @param asid Address Space ID.
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| 195 | */
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| 196 | void tlb_invalidate_asid(asid_t asid)
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| 197 | {
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| 198 | /* TODO: write asid to some Context register and encode the register in second parameter below. */
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| 199 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
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| 200 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
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| 201 | }
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| 202 |
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[4512d7e] | 203 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
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[dbb6886] | 204 | *
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| 205 | * @param asid Address Space ID.
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[4512d7e] | 206 | * @param page First page which to sweep out from ITLB and DTLB.
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| 207 | * @param cnt Number of ITLB and DTLB entries to invalidate.
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[dbb6886] | 208 | */
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[7f1c620] | 209 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
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[dbb6886] | 210 | {
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[4512d7e] | 211 | int i;
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| 212 |
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| 213 | for (i = 0; i < cnt; i++) {
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| 214 | /* TODO: write asid to some Context register and encode the register in second parameter below. */
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| 215 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
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| 216 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
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| 217 | }
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[dbb6886] | 218 | }
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[b45c443] | 219 |
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[10b890b] | 220 | /** @}
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[b45c443] | 221 | */
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