source: mainline/kernel/arch/sparc64/src/mm/sun4v/tsb.c

Last change on this file was c5429fe, checked in by Jakub Jermar <jakub@…>, 7 years ago

Disambiguate architecture specific doxygroups
  • Property mode set to 100644
File size: 4.6 KB
Line 
1/*
2 * Copyright (c) 2006 Jakub Jermar
3 * Copyright (c) 2009 Pavel Rimsky
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @addtogroup kernel_sparc64_mm
31 * @{
32 */
33/** @file
34 */
35
36#include <arch/mm/tsb.h>
37#include <arch/mm/pagesize.h>
38#include <arch/mm/tlb.h>
39#include <arch/mm/page.h>
40#include <barrier.h>
41#include <assert.h>
42#include <mm/as.h>
43#include <typedefs.h>
44#include <macros.h>
45
46/** Invalidate portion of TSB.
47 *
48 * We assume that the address space is already locked. Note that respective
49 * portions of both TSBs are invalidated at a time.
50 *
51 * @param as Address space.
52 * @param page First page to invalidate in TSB.
53 * @param pages Number of pages to invalidate. Value of (count_t) -1 means the
54 * whole TSB.
55 */
56void tsb_invalidate(as_t *as, uintptr_t page, size_t pages)
57{
58 tsb_entry_t *tsb;
59 size_t i0, i;
60 size_t cnt;
61
62 assert(as->arch.tsb_description.tsb_base);
63
64 i0 = (page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK;
65
66 if (pages == (size_t) -1 || pages > TSB_ENTRY_COUNT)
67 cnt = TSB_ENTRY_COUNT;
68 else
69 cnt = pages;
70
71 tsb = (tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base);
72 for (i = 0; i < cnt; i++)
73 tsb[(i0 + i) & TSB_ENTRY_MASK].data.v = false;
74}
75
76/** Copy software PTE to ITSB.
77 *
78 * @param t Software PTE.
79 */
80void itsb_pte_copy(pte_t *t)
81{
82 as_t *as;
83 tsb_entry_t *tsb;
84 tsb_entry_t *tte;
85 size_t index;
86
87 as = t->as;
88 index = (t->page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK;
89
90 tsb = (tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base);
91 tte = &tsb[index];
92
93 /*
94 * We use write barriers to make sure that the TSB load
95 * won't use inconsistent data or that the fault will
96 * be repeated.
97 */
98
99 tte->data.v = false;
100
101 write_barrier();
102
103 tte->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
104
105 tte->data.value = 0;
106 tte->data.nfo = false;
107 tte->data.ra = t->frame >> MMU_FRAME_WIDTH;
108 tte->data.ie = false;
109 tte->data.e = false;
110 tte->data.cp = t->c; /* cp as cache in phys.-idxed, c as cacheable */
111 tte->data.cv = false;
112 tte->data.p = t->k; /* p as privileged, k as kernel */
113 tte->data.x = true;
114 tte->data.w = false;
115 tte->data.size = PAGESIZE_8K;
116
117 write_barrier();
118
119 tte->data.v = t->p; /* v as valid, p as present */
120}
121
122/** Copy software PTE to DTSB.
123 *
124 * @param t Software PTE.
125 * @param ro If true, the mapping is copied read-only.
126 */
127void dtsb_pte_copy(pte_t *t, bool ro)
128{
129 as_t *as;
130 tsb_entry_t *tsb;
131 tsb_entry_t *tte;
132 size_t index;
133
134 as = t->as;
135 index = (t->page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK;
136 tsb = (tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base);
137 tte = &tsb[index];
138
139 /*
140 * We use write barriers to make sure that the TSB load
141 * won't use inconsistent data or that the fault will
142 * be repeated.
143 */
144
145 tte->data.v = false;
146
147 write_barrier();
148
149 tte->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
150
151 tte->data.value = 0;
152 tte->data.nfo = false;
153 tte->data.ra = t->frame >> MMU_FRAME_WIDTH;
154 tte->data.ie = false;
155 tte->data.e = false;
156 tte->data.cp = t->c; /* cp as cache in phys.-idxed, c as cacheable */
157#ifdef CONFIG_VIRT_IDX_DCACHE
158 tte->data.cv = t->c;
159#endif /* CONFIG_VIRT_IDX_DCACHE */
160 tte->data.p = t->k; /* p as privileged, k as kernel */
161 tte->data.x = true;
162 tte->data.w = ro ? false : t->w;
163 tte->data.size = PAGESIZE_8K;
164
165 write_barrier();
166
167 tte->data.v = t->p; /* v as valid, p as present */
168}
169
170/** @}
171 */
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