[ef67bab] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2006 Jakub Jermar
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[8c2214e] | 3 | * Copyright (c) 2009 Pavel Rimsky
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[ef67bab] | 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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| 29 |
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[ed166f7] | 30 | /** @addtogroup sparc64mm
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[b45c443] | 31 | * @{
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| 32 | */
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| 33 | /** @file
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| 34 | */
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| 35 |
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[ef67bab] | 36 | #include <arch/mm/as.h>
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[8c2214e] | 37 | #include <arch/mm/pagesize.h>
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[ed166f7] | 38 | #include <arch/mm/tlb.h>
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[b3f8fb7] | 39 | #include <genarch/mm/page_ht.h>
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[d0a0f12] | 40 | #include <genarch/mm/asid_fifo.h>
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[57da95c] | 41 | #include <debug.h>
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[a9ac978] | 42 | #include <config.h>
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[8c2214e] | 43 | #include <arch/sun4v/hypercall.h>
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[57da95c] | 44 |
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| 45 | #ifdef CONFIG_TSB
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[da1bafb] | 46 |
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[57da95c] | 47 | #include <arch/mm/tsb.h>
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[29b2bbf] | 48 | #include <arch/asm.h>
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| 49 | #include <mm/frame.h>
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| 50 | #include <bitops.h>
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| 51 | #include <macros.h>
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[b6f3e7e] | 52 | #include <memstr.h>
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[da1bafb] | 53 |
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[92778f2] | 54 | #endif /* CONFIG_TSB */
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| 55 |
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[ef67bab] | 56 | /** Architecture dependent address space init. */
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| 57 | void as_arch_init(void)
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| 58 | {
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[a9ac978] | 59 | if (config.cpu_active == 1) {
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| 60 | as_operations = &as_ht_operations;
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| 61 | asid_fifo_init();
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| 62 | }
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[ef67bab] | 63 | }
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[b45c443] | 64 |
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[da1bafb] | 65 | int as_constructor_arch(as_t *as, unsigned int flags)
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[29b2bbf] | 66 | {
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| 67 | #ifdef CONFIG_TSB
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[cd3b380] | 68 | uintptr_t tsb =
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| 69 | frame_alloc(SIZE2FRAMES(TSB_ENTRY_COUNT * sizeof(tsb_entry_t)),
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| 70 | flags, 0);
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[29b2bbf] | 71 | if (!tsb)
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| 72 | return -1;
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[da1bafb] | 73 |
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[ba50a34] | 74 | as->arch.tsb_description.page_size = PAGESIZE_8K;
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| 75 | as->arch.tsb_description.associativity = 1;
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| 76 | as->arch.tsb_description.num_ttes = TSB_ENTRY_COUNT;
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| 77 | as->arch.tsb_description.pgsize_mask = 1 << PAGESIZE_8K;
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| 78 | as->arch.tsb_description.tsb_base = tsb;
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| 79 | as->arch.tsb_description.reserved = 0;
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| 80 | as->arch.tsb_description.context = 0;
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[da1bafb] | 81 |
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[ba50a34] | 82 | memsetb((void *) PA2KA(as->arch.tsb_description.tsb_base),
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| 83 | TSB_ENTRY_COUNT * sizeof(tsb_entry_t), 0);
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[29b2bbf] | 84 | #endif
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[da1bafb] | 85 |
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[29b2bbf] | 86 | return 0;
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| 87 | }
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| 88 |
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| 89 | int as_destructor_arch(as_t *as)
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| 90 | {
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| 91 | #ifdef CONFIG_TSB
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[cd3b380] | 92 | size_t frames = SIZE2FRAMES(TSB_ENTRY_COUNT * sizeof(tsb_entry_t));
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| 93 | frame_free(as->arch.tsb_description.tsb_base, frames);
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[da1bafb] | 94 |
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[cd3b380] | 95 | return frames;
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[29b2bbf] | 96 | #else
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| 97 | return 0;
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| 98 | #endif
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| 99 | }
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| 100 |
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[da1bafb] | 101 | int as_create_arch(as_t *as, unsigned int flags)
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[29b2bbf] | 102 | {
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| 103 | #ifdef CONFIG_TSB
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[98000fb] | 104 | tsb_invalidate(as, 0, (size_t) -1);
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[29b2bbf] | 105 | #endif
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[da1bafb] | 106 |
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[29b2bbf] | 107 | return 0;
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| 108 | }
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| 109 |
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[771cd22] | 110 | /** Perform sparc64-specific tasks when an address space becomes active on the
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| 111 | * processor.
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[57da95c] | 112 | *
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| 113 | * Install ASID and map TSBs.
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| 114 | *
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| 115 | * @param as Address space.
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[da1bafb] | 116 | *
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[57da95c] | 117 | */
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[ed166f7] | 118 | void as_install_arch(as_t *as)
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| 119 | {
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[ba50a34] | 120 | mmu_secondary_context_write(as->asid);
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[da1bafb] | 121 |
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| 122 | #ifdef CONFIG_TSB
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[8c2214e] | 123 | uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
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[da1bafb] | 124 |
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[8c2214e] | 125 | ASSERT(as->arch.tsb_description.tsb_base);
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| 126 | uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base);
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[da1bafb] | 127 |
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[8c2214e] | 128 | if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
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| 129 | /*
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| 130 | * TSBs were allocated from memory not covered
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| 131 | * by the locked 4M kernel DTLB entry. We need
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| 132 | * to map both TSBs explicitly.
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[da1bafb] | 133 | *
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[8c2214e] | 134 | */
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| 135 | mmu_demap_page(tsb, 0, MMU_FLAG_DTLB);
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| 136 | dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
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| 137 | }
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| 138 |
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[da1bafb] | 139 | __hypercall_fast2(MMU_TSB_CTXNON0, 1, KA2PA(&(as->arch.tsb_description)));
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[8c2214e] | 140 | #endif
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[57da95c] | 141 | }
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| 142 |
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[771cd22] | 143 | /** Perform sparc64-specific tasks when an address space is removed from the
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| 144 | * processor.
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[57da95c] | 145 | *
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| 146 | * Demap TSBs.
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| 147 | *
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| 148 | * @param as Address space.
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[da1bafb] | 149 | *
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[57da95c] | 150 | */
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| 151 | void as_deinstall_arch(as_t *as)
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| 152 | {
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| 153 | /*
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[879585a3] | 154 | * Note that we don't and may not lock the address space. That's ok
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| 155 | * since we only read members that are currently read-only.
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| 156 | *
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| 157 | * Moreover, the as->asid is protected by asidlock, which is being held.
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[da1bafb] | 158 | *
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[57da95c] | 159 | */
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[da1bafb] | 160 |
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[57da95c] | 161 | #ifdef CONFIG_TSB
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[29b2bbf] | 162 | uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
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[da1bafb] | 163 |
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[8c2214e] | 164 | ASSERT(as->arch.tsb_description.tsb_base);
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[da1bafb] | 165 |
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[8c2214e] | 166 | uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base);
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[da1bafb] | 167 |
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[2057572] | 168 | if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
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[29b2bbf] | 169 | /*
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| 170 | * TSBs were allocated from memory not covered
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| 171 | * by the locked 4M kernel DTLB entry. We need
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| 172 | * to demap the entry installed by as_install_arch().
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[da1bafb] | 173 | *
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[29b2bbf] | 174 | */
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[8c2214e] | 175 | __hypercall_fast3(MMU_UNMAP_PERM_ADDR, tsb, 0, MMU_FLAG_DTLB);
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[57da95c] | 176 | }
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| 177 | #endif
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[ed166f7] | 178 | }
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| 179 |
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| 180 | /** @}
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[b45c443] | 181 | */
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