source: mainline/kernel/arch/sparc64/src/mm/sun4v/as.c@ b6f3e7e

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b6f3e7e was b6f3e7e, checked in by Jakub Jermar <jakub@…>, 14 years ago

Cleanup. No change in functionality.

Delegate some work to the preprocessor.
Fix including of memstr.h by code in mm/.

  • Property mode set to 100644
File size: 4.8 KB
RevLine 
[ef67bab]1/*
[df4ed85]2 * Copyright (c) 2006 Jakub Jermar
[8c2214e]3 * Copyright (c) 2009 Pavel Rimsky
[ef67bab]4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
[ed166f7]30/** @addtogroup sparc64mm
[b45c443]31 * @{
32 */
33/** @file
34 */
35
[ef67bab]36#include <arch/mm/as.h>
[8c2214e]37#include <arch/mm/pagesize.h>
[ed166f7]38#include <arch/mm/tlb.h>
[b3f8fb7]39#include <genarch/mm/page_ht.h>
[d0a0f12]40#include <genarch/mm/asid_fifo.h>
[57da95c]41#include <debug.h>
[a9ac978]42#include <config.h>
[8c2214e]43#include <arch/sun4v/hypercall.h>
[57da95c]44
45#ifdef CONFIG_TSB
[da1bafb]46
[57da95c]47#include <arch/mm/tsb.h>
[29b2bbf]48#include <arch/asm.h>
49#include <mm/frame.h>
50#include <bitops.h>
51#include <macros.h>
[b6f3e7e]52#include <memstr.h>
[da1bafb]53
[92778f2]54#endif /* CONFIG_TSB */
55
[ef67bab]56/** Architecture dependent address space init. */
57void as_arch_init(void)
58{
[a9ac978]59 if (config.cpu_active == 1) {
60 as_operations = &as_ht_operations;
61 asid_fifo_init();
62 }
[ef67bab]63}
[b45c443]64
[da1bafb]65int as_constructor_arch(as_t *as, unsigned int flags)
[29b2bbf]66{
67#ifdef CONFIG_TSB
[da1bafb]68 uint8_t order = fnzb32(
[ba50a34]69 (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH);
[da1bafb]70
[ba50a34]71 uintptr_t tsb = (uintptr_t) frame_alloc(order, flags);
[da1bafb]72
[29b2bbf]73 if (!tsb)
74 return -1;
[da1bafb]75
[ba50a34]76 as->arch.tsb_description.page_size = PAGESIZE_8K;
77 as->arch.tsb_description.associativity = 1;
78 as->arch.tsb_description.num_ttes = TSB_ENTRY_COUNT;
79 as->arch.tsb_description.pgsize_mask = 1 << PAGESIZE_8K;
80 as->arch.tsb_description.tsb_base = tsb;
81 as->arch.tsb_description.reserved = 0;
82 as->arch.tsb_description.context = 0;
[da1bafb]83
[ba50a34]84 memsetb((void *) PA2KA(as->arch.tsb_description.tsb_base),
85 TSB_ENTRY_COUNT * sizeof(tsb_entry_t), 0);
[29b2bbf]86#endif
[da1bafb]87
[29b2bbf]88 return 0;
89}
90
91int as_destructor_arch(as_t *as)
92{
93#ifdef CONFIG_TSB
[8c2214e]94 size_t cnt = (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH;
[ba50a34]95 frame_free((uintptr_t) as->arch.tsb_description.tsb_base);
[da1bafb]96
[29b2bbf]97 return cnt;
98#else
99 return 0;
100#endif
101}
102
[da1bafb]103int as_create_arch(as_t *as, unsigned int flags)
[29b2bbf]104{
105#ifdef CONFIG_TSB
[98000fb]106 tsb_invalidate(as, 0, (size_t) -1);
[29b2bbf]107#endif
[da1bafb]108
[29b2bbf]109 return 0;
110}
111
[771cd22]112/** Perform sparc64-specific tasks when an address space becomes active on the
113 * processor.
[57da95c]114 *
115 * Install ASID and map TSBs.
116 *
117 * @param as Address space.
[da1bafb]118 *
[57da95c]119 */
[ed166f7]120void as_install_arch(as_t *as)
121{
[ba50a34]122 mmu_secondary_context_write(as->asid);
[da1bafb]123
124#ifdef CONFIG_TSB
[8c2214e]125 uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
[da1bafb]126
[8c2214e]127 ASSERT(as->arch.tsb_description.tsb_base);
128 uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base);
[da1bafb]129
[8c2214e]130 if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
131 /*
132 * TSBs were allocated from memory not covered
133 * by the locked 4M kernel DTLB entry. We need
134 * to map both TSBs explicitly.
[da1bafb]135 *
[8c2214e]136 */
137 mmu_demap_page(tsb, 0, MMU_FLAG_DTLB);
138 dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
139 }
140
[da1bafb]141 __hypercall_fast2(MMU_TSB_CTXNON0, 1, KA2PA(&(as->arch.tsb_description)));
[8c2214e]142#endif
[57da95c]143}
144
[771cd22]145/** Perform sparc64-specific tasks when an address space is removed from the
146 * processor.
[57da95c]147 *
148 * Demap TSBs.
149 *
150 * @param as Address space.
[da1bafb]151 *
[57da95c]152 */
153void as_deinstall_arch(as_t *as)
154{
155 /*
[879585a3]156 * Note that we don't and may not lock the address space. That's ok
157 * since we only read members that are currently read-only.
158 *
159 * Moreover, the as->asid is protected by asidlock, which is being held.
[da1bafb]160 *
[57da95c]161 */
[da1bafb]162
[57da95c]163#ifdef CONFIG_TSB
[29b2bbf]164 uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
[da1bafb]165
[8c2214e]166 ASSERT(as->arch.tsb_description.tsb_base);
[da1bafb]167
[8c2214e]168 uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base);
[da1bafb]169
[2057572]170 if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
[29b2bbf]171 /*
172 * TSBs were allocated from memory not covered
173 * by the locked 4M kernel DTLB entry. We need
174 * to demap the entry installed by as_install_arch().
[da1bafb]175 *
[29b2bbf]176 */
[8c2214e]177 __hypercall_fast3(MMU_UNMAP_PERM_ADDR, tsb, 0, MMU_FLAG_DTLB);
[57da95c]178 }
179#endif
[ed166f7]180}
181
182/** @}
[b45c443]183 */
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