source: mainline/kernel/arch/sparc64/src/mm/sun4u/tsb.c

Last change on this file was c5429fe, checked in by Jakub Jermar <jakub@…>, 7 years ago

Disambiguate architecture specific doxygroups
  • Property mode set to 100644
File size: 4.7 KB
Line 
1/*
2 * Copyright (c) 2006 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup kernel_sparc64_mm
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/mm/tsb.h>
36#include <arch/mm/tlb.h>
37#include <arch/mm/page.h>
38#include <barrier.h>
39#include <assert.h>
40#include <mm/as.h>
41#include <typedefs.h>
42#include <macros.h>
43
44/** Invalidate portion of TSB.
45 *
46 * We assume that the address space is already locked. Note that respective
47 * portions of both TSBs are invalidated at a time.
48 *
49 * @param as Address space.
50 * @param page First page to invalidate in TSB.
51 * @param pages Number of pages to invalidate. Value of (size_t) -1 means the
52 * whole TSB.
53 */
54void tsb_invalidate(as_t *as, uintptr_t page, size_t pages)
55{
56 size_t i0;
57 size_t i;
58 size_t cnt;
59
60 assert(as->arch.itsb);
61 assert(as->arch.dtsb);
62
63 i0 = (page >> MMU_PAGE_WIDTH) & ITSB_ENTRY_MASK;
64
65 if (pages == (size_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT)
66 cnt = ITSB_ENTRY_COUNT;
67 else
68 cnt = pages * 2;
69
70 for (i = 0; i < cnt; i++) {
71 as->arch.itsb[(i0 + i) & ITSB_ENTRY_MASK].tag.invalid = true;
72 as->arch.dtsb[(i0 + i) & DTSB_ENTRY_MASK].tag.invalid = true;
73 }
74}
75
76/** Copy software PTE to ITSB.
77 *
78 * @param t Software PTE.
79 * @param index Zero if lower 8K-subpage, one if higher 8K subpage.
80 */
81void itsb_pte_copy(pte_t *t, size_t index)
82{
83 as_t *as;
84 tsb_entry_t *tte;
85 size_t entry;
86
87 assert(index <= 1);
88
89 as = t->as;
90 entry = ((t->page >> MMU_PAGE_WIDTH) + index) & ITSB_ENTRY_MASK;
91 tte = &as->arch.itsb[entry];
92
93 /*
94 * We use write barriers to make sure that the TSB load
95 * won't use inconsistent data or that the fault will
96 * be repeated.
97 */
98
99 /* Invalidate the entry (tag target has this set to 0) */
100 tte->tag.invalid = true;
101
102 write_barrier();
103
104 tte->tag.context = as->asid;
105 /* the shift is bigger than PAGE_WIDTH, do not bother with index */
106 tte->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
107 tte->data.value = 0;
108 tte->data.size = PAGESIZE_8K;
109 tte->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
110 tte->data.cp = t->c; /* cp as cache in phys.-idxed, c as cacheable */
111 tte->data.p = t->k; /* p as privileged, k as kernel */
112 tte->data.v = t->p; /* v as valid, p as present */
113
114 write_barrier();
115
116 tte->tag.invalid = false; /* mark the entry as valid */
117}
118
119/** Copy software PTE to DTSB.
120 *
121 * @param t Software PTE.
122 * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
123 * @param ro If true, the mapping is copied read-only.
124 */
125void dtsb_pte_copy(pte_t *t, size_t index, bool ro)
126{
127 as_t *as;
128 tsb_entry_t *tte;
129 size_t entry;
130
131 assert(index <= 1);
132
133 as = t->as;
134 entry = ((t->page >> MMU_PAGE_WIDTH) + index) & DTSB_ENTRY_MASK;
135 tte = &as->arch.dtsb[entry];
136
137 /*
138 * We use write barriers to make sure that the TSB load
139 * won't use inconsistent data or that the fault will
140 * be repeated.
141 */
142
143 /* Invalidate the entry (tag target has this set to 0) */
144 tte->tag.invalid = true;
145
146 write_barrier();
147
148 tte->tag.context = as->asid;
149 /* the shift is bigger than PAGE_WIDTH, do not bother with index */
150 tte->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
151 tte->data.value = 0;
152 tte->data.size = PAGESIZE_8K;
153 tte->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
154 tte->data.cp = t->c;
155#ifdef CONFIG_VIRT_IDX_DCACHE
156 tte->data.cv = t->c;
157#endif /* CONFIG_VIRT_IDX_DCACHE */
158 tte->data.p = t->k; /* p as privileged */
159 tte->data.w = ro ? false : t->w;
160 tte->data.v = t->p;
161
162 write_barrier();
163
164 tte->tag.invalid = false; /* mark the entry as valid */
165}
166
167/** @}
168 */
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