source: mainline/kernel/arch/sparc64/src/mm/sun4u/tlb.c@ 04552324

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 04552324 was 1dbc43f, checked in by Jakub Jermar <jakub@…>, 13 years ago

Unify user page fault handling in as_page_fault().

  • Remove lots of architecture-dependent boilerplate code.
  • Property mode set to 100644
File size: 14.0 KB
Line 
1/*
2 * Copyright (c) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup sparc64mm
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/mm/tlb.h>
36#include <mm/tlb.h>
37#include <mm/as.h>
38#include <mm/asid.h>
39#include <arch/mm/frame.h>
40#include <arch/mm/page.h>
41#include <arch/mm/mmu.h>
42#include <arch/interrupt.h>
43#include <interrupt.h>
44#include <arch.h>
45#include <print.h>
46#include <typedefs.h>
47#include <config.h>
48#include <arch/trap/trap.h>
49#include <arch/trap/exception.h>
50#include <panic.h>
51#include <arch/asm.h>
52#include <genarch/mm/page_ht.h>
53
54#ifdef CONFIG_TSB
55#include <arch/mm/tsb.h>
56#endif
57
58static void dtlb_pte_copy(pte_t *, size_t, bool);
59static void itlb_pte_copy(pte_t *, size_t);
60
61const char *context_encoding[] = {
62 "Primary",
63 "Secondary",
64 "Nucleus",
65 "Reserved"
66};
67
68void tlb_arch_init(void)
69{
70 /*
71 * Invalidate all non-locked DTLB and ITLB entries.
72 */
73 tlb_invalidate_all();
74
75 /*
76 * Clear both SFSRs.
77 */
78 dtlb_sfsr_write(0);
79 itlb_sfsr_write(0);
80}
81
82/** Insert privileged mapping into DMMU TLB.
83 *
84 * @param page Virtual page address.
85 * @param frame Physical frame address.
86 * @param pagesize Page size.
87 * @param locked True for permanent mappings, false otherwise.
88 * @param cacheable True if the mapping is cacheable, false otherwise.
89 */
90void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize,
91 bool locked, bool cacheable)
92{
93 tlb_tag_access_reg_t tag;
94 tlb_data_t data;
95 page_address_t pg;
96 frame_address_t fr;
97
98 pg.address = page;
99 fr.address = frame;
100
101 tag.context = ASID_KERNEL;
102 tag.vpn = pg.vpn;
103
104 dtlb_tag_access_write(tag.value);
105
106 data.value = 0;
107 data.v = true;
108 data.size = pagesize;
109 data.pfn = fr.pfn;
110 data.l = locked;
111 data.cp = cacheable;
112#ifdef CONFIG_VIRT_IDX_DCACHE
113 data.cv = cacheable;
114#endif /* CONFIG_VIRT_IDX_DCACHE */
115 data.p = true;
116 data.w = true;
117 data.g = false;
118
119 dtlb_data_in_write(data.value);
120}
121
122/** Copy PTE to TLB.
123 *
124 * @param t Page Table Entry to be copied.
125 * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
126 * @param ro If true, the entry will be created read-only, regardless
127 * of its w field.
128 */
129void dtlb_pte_copy(pte_t *t, size_t index, bool ro)
130{
131 tlb_tag_access_reg_t tag;
132 tlb_data_t data;
133 page_address_t pg;
134 frame_address_t fr;
135
136 pg.address = t->page + (index << MMU_PAGE_WIDTH);
137 fr.address = t->frame + (index << MMU_PAGE_WIDTH);
138
139 tag.value = 0;
140 tag.context = t->as->asid;
141 tag.vpn = pg.vpn;
142
143 dtlb_tag_access_write(tag.value);
144
145 data.value = 0;
146 data.v = true;
147 data.size = PAGESIZE_8K;
148 data.pfn = fr.pfn;
149 data.l = false;
150 data.cp = t->c;
151#ifdef CONFIG_VIRT_IDX_DCACHE
152 data.cv = t->c;
153#endif /* CONFIG_VIRT_IDX_DCACHE */
154 data.p = t->k; /* p like privileged */
155 data.w = ro ? false : t->w;
156 data.g = t->g;
157
158 dtlb_data_in_write(data.value);
159}
160
161/** Copy PTE to ITLB.
162 *
163 * @param t Page Table Entry to be copied.
164 * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
165 */
166void itlb_pte_copy(pte_t *t, size_t index)
167{
168 tlb_tag_access_reg_t tag;
169 tlb_data_t data;
170 page_address_t pg;
171 frame_address_t fr;
172
173 pg.address = t->page + (index << MMU_PAGE_WIDTH);
174 fr.address = t->frame + (index << MMU_PAGE_WIDTH);
175
176 tag.value = 0;
177 tag.context = t->as->asid;
178 tag.vpn = pg.vpn;
179
180 itlb_tag_access_write(tag.value);
181
182 data.value = 0;
183 data.v = true;
184 data.size = PAGESIZE_8K;
185 data.pfn = fr.pfn;
186 data.l = false;
187 data.cp = t->c;
188 data.p = t->k; /* p like privileged */
189 data.w = false;
190 data.g = t->g;
191
192 itlb_data_in_write(data.value);
193}
194
195/** ITLB miss handler. */
196void fast_instruction_access_mmu_miss(sysarg_t unused, istate_t *istate)
197{
198 uintptr_t page_16k = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
199 size_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE;
200 pte_t *t;
201
202 t = page_mapping_find(AS, page_16k, true);
203 if (t && PTE_EXECUTABLE(t)) {
204 /*
205 * The mapping was found in the software page hash table.
206 * Insert it into ITLB.
207 */
208 t->a = true;
209 itlb_pte_copy(t, index);
210#ifdef CONFIG_TSB
211 itsb_pte_copy(t, index);
212#endif
213 } else {
214 /*
215 * Forward the page fault to the address space page fault
216 * handler.
217 */
218 as_page_fault(page_16k, PF_ACCESS_EXEC, istate);
219 }
220}
221
222/** DTLB miss handler.
223 *
224 * Note that some faults (e.g. kernel faults) were already resolved by the
225 * low-level, assembly language part of the fast_data_access_mmu_miss handler.
226 *
227 * @param tag Content of the TLB Tag Access register as it existed
228 * when the trap happened. This is to prevent confusion
229 * created by clobbered Tag Access register during a nested
230 * DTLB miss.
231 * @param istate Interrupted state saved on the stack.
232 */
233void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate)
234{
235 uintptr_t page_8k;
236 uintptr_t page_16k;
237 size_t index;
238 pte_t *t;
239 as_t *as = AS;
240
241 page_8k = (uint64_t) tag.vpn << MMU_PAGE_WIDTH;
242 page_16k = ALIGN_DOWN(page_8k, PAGE_SIZE);
243 index = tag.vpn % MMU_PAGES_PER_PAGE;
244
245 if (tag.context == ASID_KERNEL) {
246 if (!tag.vpn) {
247 /* NULL access in kernel */
248 panic("NULL pointer dereference.");
249 } else if (page_8k >= end_of_identity) {
250 /* Kernel non-identity. */
251 as = AS_KERNEL;
252 } else {
253 panic("Unexpected kernel page fault.");
254 }
255 }
256
257 t = page_mapping_find(as, page_16k, true);
258 if (t) {
259 /*
260 * The mapping was found in the software page hash table.
261 * Insert it into DTLB.
262 */
263 t->a = true;
264 dtlb_pte_copy(t, index, true);
265#ifdef CONFIG_TSB
266 dtsb_pte_copy(t, index, true);
267#endif
268 } else {
269 /*
270 * Forward the page fault to the address space page fault
271 * handler.
272 */
273 as_page_fault(page_16k, PF_ACCESS_READ, istate);
274 }
275}
276
277/** DTLB protection fault handler.
278 *
279 * @param tag Content of the TLB Tag Access register as it existed
280 * when the trap happened. This is to prevent confusion
281 * created by clobbered Tag Access register during a nested
282 * DTLB miss.
283 * @param istate Interrupted state saved on the stack.
284 */
285void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate)
286{
287 uintptr_t page_16k;
288 size_t index;
289 pte_t *t;
290 as_t *as = AS;
291
292 page_16k = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
293 index = tag.vpn % MMU_PAGES_PER_PAGE; /* 16K-page emulation */
294
295 if (tag.context == ASID_KERNEL)
296 as = AS_KERNEL;
297
298 t = page_mapping_find(as, page_16k, true);
299 if (t && PTE_WRITABLE(t)) {
300 /*
301 * The mapping was found in the software page hash table and is
302 * writable. Demap the old mapping and insert an updated mapping
303 * into DTLB.
304 */
305 t->a = true;
306 t->d = true;
307 dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY,
308 page_16k + index * MMU_PAGE_SIZE);
309 dtlb_pte_copy(t, index, false);
310#ifdef CONFIG_TSB
311 dtsb_pte_copy(t, index, false);
312#endif
313 } else {
314 /*
315 * Forward the page fault to the address space page fault
316 * handler.
317 */
318 as_page_fault(page_16k, PF_ACCESS_WRITE, istate);
319 }
320}
321
322/** Print TLB entry (for debugging purposes).
323 *
324 * The diag field has been left out in order to make this function more generic
325 * (there is no diag field in US3 architeture).
326 *
327 * @param i TLB entry number
328 * @param t TLB entry tag
329 * @param d TLB entry data
330 */
331static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d)
332{
333 printf("%u: vpn=%#" PRIx64 ", context=%u, v=%u, size=%u, nfo=%u, "
334 "ie=%u, soft2=%#x, pfn=%#x, soft=%#x, l=%u, "
335 "cp=%u, cv=%u, e=%u, p=%u, w=%u, g=%u\n", i, (uint64_t) t.vpn,
336 t.context, d.v, d.size, d.nfo, d.ie, d.soft2,
337 d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
338}
339
340#if defined (US)
341
342/** Print contents of both TLBs. */
343void tlb_print(void)
344{
345 int i;
346 tlb_data_t d;
347 tlb_tag_read_reg_t t;
348
349 printf("I-TLB contents:\n");
350 for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
351 d.value = itlb_data_access_read(i);
352 t.value = itlb_tag_read_read(i);
353 print_tlb_entry(i, t, d);
354 }
355
356 printf("D-TLB contents:\n");
357 for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
358 d.value = dtlb_data_access_read(i);
359 t.value = dtlb_tag_read_read(i);
360 print_tlb_entry(i, t, d);
361 }
362}
363
364#elif defined (US3)
365
366/** Print contents of all TLBs. */
367void tlb_print(void)
368{
369 int i;
370 tlb_data_t d;
371 tlb_tag_read_reg_t t;
372
373 printf("TLB_ISMALL contents:\n");
374 for (i = 0; i < tlb_ismall_size(); i++) {
375 d.value = dtlb_data_access_read(TLB_ISMALL, i);
376 t.value = dtlb_tag_read_read(TLB_ISMALL, i);
377 print_tlb_entry(i, t, d);
378 }
379
380 printf("TLB_IBIG contents:\n");
381 for (i = 0; i < tlb_ibig_size(); i++) {
382 d.value = dtlb_data_access_read(TLB_IBIG, i);
383 t.value = dtlb_tag_read_read(TLB_IBIG, i);
384 print_tlb_entry(i, t, d);
385 }
386
387 printf("TLB_DSMALL contents:\n");
388 for (i = 0; i < tlb_dsmall_size(); i++) {
389 d.value = dtlb_data_access_read(TLB_DSMALL, i);
390 t.value = dtlb_tag_read_read(TLB_DSMALL, i);
391 print_tlb_entry(i, t, d);
392 }
393
394 printf("TLB_DBIG_1 contents:\n");
395 for (i = 0; i < tlb_dbig_size(); i++) {
396 d.value = dtlb_data_access_read(TLB_DBIG_0, i);
397 t.value = dtlb_tag_read_read(TLB_DBIG_0, i);
398 print_tlb_entry(i, t, d);
399 }
400
401 printf("TLB_DBIG_2 contents:\n");
402 for (i = 0; i < tlb_dbig_size(); i++) {
403 d.value = dtlb_data_access_read(TLB_DBIG_1, i);
404 t.value = dtlb_tag_read_read(TLB_DBIG_1, i);
405 print_tlb_entry(i, t, d);
406 }
407}
408
409#endif
410
411void describe_dmmu_fault(void)
412{
413 tlb_sfsr_reg_t sfsr;
414 uintptr_t sfar;
415
416 sfsr.value = dtlb_sfsr_read();
417 sfar = dtlb_sfar_read();
418
419#if defined (US)
420 printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "
421 "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w,
422 sfsr.ow, sfsr.fv);
423#elif defined (US3)
424 printf("DTLB SFSR: nf=%d, asi=%#x, tm=%d, ft=%#x, e=%d, ct=%d, pr=%d, "
425 "w=%d, ow=%d, fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft,
426 sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
427#endif
428
429 printf("DTLB SFAR: address=%p\n", (void *) sfar);
430
431 dtlb_sfsr_write(0);
432}
433
434void dump_sfsr_and_sfar(void)
435{
436 tlb_sfsr_reg_t sfsr;
437 uintptr_t sfar;
438
439 sfsr.value = dtlb_sfsr_read();
440 sfar = dtlb_sfar_read();
441
442#if defined (US)
443 printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "
444 "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w,
445 sfsr.ow, sfsr.fv);
446#elif defined (US3)
447 printf("DTLB SFSR: nf=%d, asi=%#x, tm=%d, ft=%#x, e=%d, ct=%d, pr=%d, "
448 "w=%d, ow=%d, fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft,
449 sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
450#endif
451
452 printf("DTLB SFAR: address=%p\n", (void *) sfar);
453
454 dtlb_sfsr_write(0);
455}
456
457#if defined (US)
458/** Invalidate all unlocked ITLB and DTLB entries. */
459void tlb_invalidate_all(void)
460{
461 int i;
462
463 /*
464 * Walk all ITLB and DTLB entries and remove all unlocked mappings.
465 *
466 * The kernel doesn't use global mappings so any locked global mappings
467 * found must have been created by someone else. Their only purpose now
468 * is to collide with proper mappings. Invalidate immediately. It should
469 * be safe to invalidate them as late as now.
470 */
471
472 tlb_data_t d;
473 tlb_tag_read_reg_t t;
474
475 for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
476 d.value = itlb_data_access_read(i);
477 if (!d.l || d.g) {
478 t.value = itlb_tag_read_read(i);
479 d.v = false;
480 itlb_tag_access_write(t.value);
481 itlb_data_access_write(i, d.value);
482 }
483 }
484
485 for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
486 d.value = dtlb_data_access_read(i);
487 if (!d.l || d.g) {
488 t.value = dtlb_tag_read_read(i);
489 d.v = false;
490 dtlb_tag_access_write(t.value);
491 dtlb_data_access_write(i, d.value);
492 }
493 }
494
495}
496
497#elif defined (US3)
498
499/** Invalidate all unlocked ITLB and DTLB entries. */
500void tlb_invalidate_all(void)
501{
502 itlb_demap(TLB_DEMAP_ALL, 0, 0);
503 dtlb_demap(TLB_DEMAP_ALL, 0, 0);
504}
505
506#endif
507
508/** Invalidate all ITLB and DTLB entries that belong to specified ASID
509 * (Context).
510 *
511 * @param asid Address Space ID.
512 */
513void tlb_invalidate_asid(asid_t asid)
514{
515 tlb_context_reg_t pc_save, ctx;
516
517 /* switch to nucleus because we are mapped by the primary context */
518 nucleus_enter();
519
520 ctx.v = pc_save.v = mmu_primary_context_read();
521 ctx.context = asid;
522 mmu_primary_context_write(ctx.v);
523
524 itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
525 dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
526
527 mmu_primary_context_write(pc_save.v);
528
529 nucleus_leave();
530}
531
532/** Invalidate all ITLB and DTLB entries for specified page range in specified
533 * address space.
534 *
535 * @param asid Address Space ID.
536 * @param page First page which to sweep out from ITLB and DTLB.
537 * @param cnt Number of ITLB and DTLB entries to invalidate.
538 */
539void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
540{
541 unsigned int i;
542 tlb_context_reg_t pc_save, ctx;
543
544 /* switch to nucleus because we are mapped by the primary context */
545 nucleus_enter();
546
547 ctx.v = pc_save.v = mmu_primary_context_read();
548 ctx.context = asid;
549 mmu_primary_context_write(ctx.v);
550
551 for (i = 0; i < cnt * MMU_PAGES_PER_PAGE; i++) {
552 itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY,
553 page + i * MMU_PAGE_SIZE);
554 dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY,
555 page + i * MMU_PAGE_SIZE);
556 }
557
558 mmu_primary_context_write(pc_save.v);
559
560 nucleus_leave();
561}
562
563/** @}
564 */
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