source: mainline/kernel/arch/sparc64/src/mm/sun4u/as.c

Last change on this file was b169619, checked in by Jiří Zárevúcky <zarevucky.jiri@…>, 21 months ago

Deduplicate mem functions

There are a number of functions which are copied between
kernel, libc, and potentially boot too. mem*() functions
are first such offenders. All this duplicate code will
be moved to directory 'common'.

  • Property mode set to 100644
File size: 5.8 KB
RevLine 
[ef67bab]1/*
[df4ed85]2 * Copyright (c) 2006 Jakub Jermar
[ef67bab]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[c5429fe]29/** @addtogroup kernel_sparc64_mm
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[ef67bab]35#include <arch/mm/as.h>
[ed166f7]36#include <arch/mm/tlb.h>
[63e27ef]37#include <assert.h>
38#include <config.h>
[b3f8fb7]39#include <genarch/mm/page_ht.h>
[d0a0f12]40#include <genarch/mm/asid_fifo.h>
[57da95c]41
42#ifdef CONFIG_TSB
[da1bafb]43
[57da95c]44#include <arch/mm/tsb.h>
[29b2bbf]45#include <arch/asm.h>
46#include <mm/frame.h>
47#include <bitops.h>
48#include <macros.h>
[b169619]49#include <memw.h>
[da1bafb]50
[92778f2]51#endif /* CONFIG_TSB */
52
[ef67bab]53/** Architecture dependent address space init. */
54void as_arch_init(void)
55{
[a9ac978]56 if (config.cpu_active == 1) {
57 as_operations = &as_ht_operations;
58 asid_fifo_init();
59 }
[ef67bab]60}
[b45c443]61
[b7fd2a0]62errno_t as_constructor_arch(as_t *as, unsigned int flags)
[29b2bbf]63{
64#ifdef CONFIG_TSB
[482f968]65 uintptr_t tsb_base = frame_alloc(TSB_FRAMES, FRAME_LOWMEM | flags,
66 TSB_SIZE - 1);
[e08162b]67 if (!tsb_base)
[ee6f434]68 return ENOMEM;
[e08162b]69
70 tsb_entry_t *tsb = (tsb_entry_t *) PA2KA(tsb_base);
71 memsetb(tsb, TSB_SIZE, 0);
[a35b458]72
[cd3b380]73 as->arch.itsb = tsb;
74 as->arch.dtsb = tsb + ITSB_ENTRY_COUNT;
[29b2bbf]75#endif
[a35b458]76
[ee6f434]77 return EOK;
[29b2bbf]78}
79
80int as_destructor_arch(as_t *as)
81{
82#ifdef CONFIG_TSB
[e08162b]83 frame_free(KA2PA((uintptr_t) as->arch.itsb), TSB_FRAMES);
[a35b458]84
[e08162b]85 return TSB_FRAMES;
[29b2bbf]86#else
87 return 0;
88#endif
89}
90
[b7fd2a0]91errno_t as_create_arch(as_t *as, unsigned int flags)
[29b2bbf]92{
93#ifdef CONFIG_TSB
[98000fb]94 tsb_invalidate(as, 0, (size_t) -1);
[29b2bbf]95#endif
[a35b458]96
[29b2bbf]97 return 0;
98}
99
[771cd22]100/** Perform sparc64-specific tasks when an address space becomes active on the
101 * processor.
[57da95c]102 *
103 * Install ASID and map TSBs.
104 *
105 * @param as Address space.
106 */
[ed166f7]107void as_install_arch(as_t *as)
108{
109 tlb_context_reg_t ctx;
[a35b458]110
[57da95c]111 /*
[879585a3]112 * Note that we don't and may not lock the address space. That's ok
113 * since we only read members that are currently read-only.
114 *
115 * Moreover, the as->asid is protected by asidlock, which is being held.
[da1bafb]116 *
[57da95c]117 */
[a35b458]118
[ed166f7]119 /*
[879585a3]120 * Write ASID to secondary context register. The primary context
121 * register has to be set from TL>0 so it will be filled from the
122 * secondary context register from the TL=1 code just before switch to
123 * userspace.
[da1bafb]124 *
[ed166f7]125 */
126 ctx.v = 0;
127 ctx.context = as->asid;
128 mmu_secondary_context_write(ctx.v);
[a35b458]129
[da1bafb]130#ifdef CONFIG_TSB
[29b2bbf]131 uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
[a35b458]132
[63e27ef]133 assert(as->arch.itsb);
134 assert(as->arch.dtsb);
[a35b458]135
[29b2bbf]136 uintptr_t tsb = (uintptr_t) as->arch.itsb;
[a35b458]137
[e08162b]138 if (!overlaps(tsb, TSB_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
[57da95c]139 /*
[29b2bbf]140 * TSBs were allocated from memory not covered
141 * by the locked 4M kernel DTLB entry. We need
142 * to map both TSBs explicitly.
[da1bafb]143 *
[57da95c]144 */
[29b2bbf]145 dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
146 dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
[57da95c]147 }
[a35b458]148
[29b2bbf]149 /*
150 * Setup TSB Base registers.
[da1bafb]151 *
[29b2bbf]152 */
[e08162b]153 tsb_base_reg_t tsb_base_reg;
[a35b458]154
[e08162b]155 tsb_base_reg.value = 0;
156 tsb_base_reg.size = TSB_BASE_REG_SIZE;
157 tsb_base_reg.split = 0;
[a35b458]158
[e08162b]159 tsb_base_reg.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH;
160 itsb_base_write(tsb_base_reg.value);
161 tsb_base_reg.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH;
162 dtsb_base_write(tsb_base_reg.value);
[a35b458]163
[965dc18]164#if defined (US3)
165 /*
166 * Clear the extension registers.
167 * In HelenOS, primary and secondary context registers contain
168 * equal values and kernel misses (context 0, ie. the nucleus context)
169 * are excluded from the TSB miss handler, so it makes no sense
170 * to have separate TSBs for primary, secondary and nucleus contexts.
171 * Clearing the extension registers will ensure that the value of the
172 * TSB Base register will be used as an address of TSB, making the code
[da1bafb]173 * compatible with the US port.
174 *
[965dc18]175 */
176 itsb_primary_extension_write(0);
177 itsb_nucleus_extension_write(0);
178 dtsb_primary_extension_write(0);
179 dtsb_secondary_extension_write(0);
180 dtsb_nucleus_extension_write(0);
181#endif
[57da95c]182#endif
183}
184
[771cd22]185/** Perform sparc64-specific tasks when an address space is removed from the
186 * processor.
[57da95c]187 *
188 * Demap TSBs.
189 *
190 * @param as Address space.
191 */
192void as_deinstall_arch(as_t *as)
193{
194 /*
[879585a3]195 * Note that we don't and may not lock the address space. That's ok
196 * since we only read members that are currently read-only.
197 *
198 * Moreover, the as->asid is protected by asidlock, which is being held.
[da1bafb]199 *
[57da95c]200 */
[a35b458]201
[57da95c]202#ifdef CONFIG_TSB
[29b2bbf]203 uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
[a35b458]204
[63e27ef]205 assert(as->arch.itsb);
206 assert(as->arch.dtsb);
[a35b458]207
[29b2bbf]208 uintptr_t tsb = (uintptr_t) as->arch.itsb;
[a35b458]209
[e08162b]210 if (!overlaps(tsb, TSB_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
[29b2bbf]211 /*
212 * TSBs were allocated from memory not covered
213 * by the locked 4M kernel DTLB entry. We need
214 * to demap the entry installed by as_install_arch().
215 */
216 dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
[57da95c]217 }
218#endif
[ed166f7]219}
220
221/** @}
[b45c443]222 */
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