source: mainline/kernel/arch/sparc64/src/mm/cache.S@ 9a7a970

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 9a7a970 was 9a7a970, checked in by Jakub Jermar <jakub@…>, 18 years ago

Move one MEMBAR instruction from a delay slot,
which is, due to SF Erratum #51, a potentionally
dangerous place for a MEMBAR to be.

  • Property mode set to 100644
File size: 2.8 KB
Line 
1/*
2 * Copyright (c) 2006 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/arch.h>
30
31#define DCACHE_SIZE (16 * 1024)
32#define DCACHE_LINE_SIZE 32
33
34#define DCACHE_TAG_SHIFT 2
35
36.register %g2, #scratch
37.register %g3, #scratch
38
39/** Flush the whole D-cache. */
40.global dcache_flush
41dcache_flush:
42 set (DCACHE_SIZE - DCACHE_LINE_SIZE), %g1
43 stxa %g0, [%g1] ASI_DCACHE_TAG
440: membar #Sync
45 subcc %g1, DCACHE_LINE_SIZE, %g1
46 bnz,pt %xcc, 0b
47 stxa %g0, [%g1] ASI_DCACHE_TAG
48 membar #Sync
49 retl
50 ! beware SF Erratum #51, do not put the MEMBAR here
51 nop
52
53/** Flush only D-cache lines of one virtual color.
54 *
55 * @param o0 Virtual color to be flushed.
56 */
57.global dcache_flush_color
58dcache_flush_color:
59 mov (DCACHE_SIZE / DCACHE_LINE_SIZE) / 2, %g1
60 set DCACHE_SIZE / 2, %g2
61 sllx %g2, %o0, %g2
62 sub %g2, DCACHE_LINE_SIZE, %g2
630: stxa %g0, [%g2] ASI_DCACHE_TAG
64 membar #Sync
65 subcc %g1, 1, %g1
66 bnz,pt %xcc, 0b
67 sub %g2, DCACHE_LINE_SIZE, %g2
68 retl
69 nop
70
71/** Flush only D-cache lines of one virtual color and one tag.
72 *
73 * @param o0 Virtual color to lookup the tag.
74 * @param o1 Tag of the cachelines to be flushed.
75 */
76.global dcache_flush_tag
77dcache_flush_tag:
78 mov (DCACHE_SIZE / DCACHE_LINE_SIZE) / 2, %g1
79 set DCACHE_SIZE / 2, %g2
80 sllx %g2, %o0, %g2
81 sub %g2, DCACHE_LINE_SIZE, %g2
820: ldxa [%g2] ASI_DCACHE_TAG, %g3
83 srlx %g3, DCACHE_TAG_SHIFT, %g3
84 cmp %g3, %o1
85 bnz 1f
86 nop
87 stxa %g0, [%g2] ASI_DCACHE_TAG
88 membar #Sync
891: subcc %g1, 1, %g1
90 bnz,pt %xcc, 0b
91 sub %g2, DCACHE_LINE_SIZE, %g2
92 retl
93 nop
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