| 1 | /*
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| 2 | * Copyright (c) 2006 Jakub Jermar
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup sparc64mm
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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| 35 | #include <arch/mm/as.h>
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| 36 | #include <arch/mm/tlb.h>
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| 37 | #include <genarch/mm/page_ht.h>
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| 38 | #include <genarch/mm/asid_fifo.h>
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| 39 | #include <debug.h>
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| 40 | #include <config.h>
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| 41 |
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| 42 | #ifdef CONFIG_TSB
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| 43 | #include <arch/mm/tsb.h>
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| 44 | #include <arch/memstr.h>
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| 45 | #include <arch/asm.h>
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| 46 | #include <mm/frame.h>
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| 47 | #include <bitops.h>
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| 48 | #include <macros.h>
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| 49 | #endif /* CONFIG_TSB */
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| 50 |
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| 51 | /** Architecture dependent address space init. */
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| 52 | void as_arch_init(void)
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| 53 | {
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| 54 | if (config.cpu_active == 1) {
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| 55 | as_operations = &as_ht_operations;
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| 56 | asid_fifo_init();
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| 57 | }
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| 58 | }
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| 59 |
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| 60 | int as_constructor_arch(as_t *as, int flags)
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| 61 | {
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| 62 | #ifdef CONFIG_TSB
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| 63 | /*
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| 64 | * The order must be calculated with respect to the emulated
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| 65 | * 16K page size.
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| 66 | */
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| 67 | int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
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| 68 | sizeof(tsb_entry_t)) >> FRAME_WIDTH);
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| 69 |
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| 70 | uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA);
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| 71 |
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| 72 | if (!tsb)
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| 73 | return -1;
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| 74 |
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| 75 | as->arch.itsb = (tsb_entry_t *) tsb;
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| 76 | as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT *
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| 77 | sizeof(tsb_entry_t));
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| 78 |
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| 79 | memsetb(as->arch.itsb,
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| 80 | (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0);
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| 81 | #endif
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| 82 | return 0;
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| 83 | }
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| 84 |
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| 85 | int as_destructor_arch(as_t *as)
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| 86 | {
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| 87 | #ifdef CONFIG_TSB
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| 88 | /*
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| 89 | * The count must be calculated with respect to the emualted 16K page
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| 90 | * size.
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| 91 | */
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| 92 | count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
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| 93 | sizeof(tsb_entry_t)) >> FRAME_WIDTH;
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| 94 | frame_free(KA2PA((uintptr_t) as->arch.itsb));
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| 95 | return cnt;
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| 96 | #else
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| 97 | return 0;
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| 98 | #endif
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| 99 | }
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| 100 |
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| 101 | int as_create_arch(as_t *as, int flags)
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| 102 | {
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| 103 | #ifdef CONFIG_TSB
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| 104 | tsb_invalidate(as, 0, (count_t) -1);
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| 105 | #endif
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| 106 | return 0;
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| 107 | }
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| 108 |
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| 109 | /** Perform sparc64-specific tasks when an address space becomes active on the
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| 110 | * processor.
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| 111 | *
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| 112 | * Install ASID and map TSBs.
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| 113 | *
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| 114 | * @param as Address space.
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| 115 | */
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| 116 | void as_install_arch(as_t *as)
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| 117 | {
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| 118 | tlb_context_reg_t ctx;
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| 119 |
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| 120 | /*
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| 121 | * Note that we don't and may not lock the address space. That's ok
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| 122 | * since we only read members that are currently read-only.
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| 123 | *
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| 124 | * Moreover, the as->asid is protected by asidlock, which is being held.
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| 125 | */
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| 126 |
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| 127 | /*
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| 128 | * Write ASID to secondary context register. The primary context
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| 129 | * register has to be set from TL>0 so it will be filled from the
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| 130 | * secondary context register from the TL=1 code just before switch to
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| 131 | * userspace.
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| 132 | */
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| 133 | ctx.v = 0;
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| 134 | ctx.context = as->asid;
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| 135 | mmu_secondary_context_write(ctx.v);
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| 136 |
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| 137 | #ifdef CONFIG_TSB
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| 138 | uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
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| 139 |
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| 140 | ASSERT(as->arch.itsb && as->arch.dtsb);
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| 141 |
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| 142 | uintptr_t tsb = (uintptr_t) as->arch.itsb;
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| 143 |
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| 144 | if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
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| 145 | /*
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| 146 | * TSBs were allocated from memory not covered
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| 147 | * by the locked 4M kernel DTLB entry. We need
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| 148 | * to map both TSBs explicitly.
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| 149 | */
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| 150 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
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| 151 | dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
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| 152 | }
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| 153 |
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| 154 | /*
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| 155 | * Setup TSB Base registers.
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| 156 | */
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| 157 | tsb_base_reg_t tsb_base;
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| 158 |
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| 159 | tsb_base.value = 0;
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| 160 | tsb_base.size = TSB_SIZE;
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| 161 | tsb_base.split = 0;
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| 162 |
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| 163 | tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH;
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| 164 | itsb_base_write(tsb_base.value);
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| 165 | tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH;
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| 166 | dtsb_base_write(tsb_base.value);
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| 167 |
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| 168 | #if defined (US3)
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| 169 | /*
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| 170 | * Clear the extension registers.
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| 171 | * In HelenOS, primary and secondary context registers contain
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| 172 | * equal values and kernel misses (context 0, ie. the nucleus context)
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| 173 | * are excluded from the TSB miss handler, so it makes no sense
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| 174 | * to have separate TSBs for primary, secondary and nucleus contexts.
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| 175 | * Clearing the extension registers will ensure that the value of the
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| 176 | * TSB Base register will be used as an address of TSB, making the code
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| 177 | * compatible with the US port.
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| 178 | */
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| 179 | itsb_primary_extension_write(0);
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| 180 | itsb_nucleus_extension_write(0);
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| 181 | dtsb_primary_extension_write(0);
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| 182 | dtsb_secondary_extension_write(0);
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| 183 | dtsb_nucleus_extension_write(0);
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| 184 | #endif
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| 185 | #endif
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| 186 | }
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| 187 |
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| 188 | /** Perform sparc64-specific tasks when an address space is removed from the
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| 189 | * processor.
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| 190 | *
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| 191 | * Demap TSBs.
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| 192 | *
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| 193 | * @param as Address space.
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| 194 | */
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| 195 | void as_deinstall_arch(as_t *as)
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| 196 | {
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| 197 |
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| 198 | /*
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| 199 | * Note that we don't and may not lock the address space. That's ok
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| 200 | * since we only read members that are currently read-only.
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| 201 | *
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| 202 | * Moreover, the as->asid is protected by asidlock, which is being held.
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| 203 | */
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| 204 |
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| 205 | #ifdef CONFIG_TSB
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| 206 | uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
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| 207 |
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| 208 | ASSERT(as->arch.itsb && as->arch.dtsb);
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| 209 |
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| 210 | uintptr_t tsb = (uintptr_t) as->arch.itsb;
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| 211 |
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| 212 | if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
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| 213 | /*
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| 214 | * TSBs were allocated from memory not covered
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| 215 | * by the locked 4M kernel DTLB entry. We need
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| 216 | * to demap the entry installed by as_install_arch().
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| 217 | */
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| 218 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
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| 219 | }
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| 220 | #endif
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| 221 | }
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| 222 |
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| 223 | /** @}
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| 224 | */
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