source: mainline/kernel/arch/sparc64/src/fpu_context.c@ 19dba2b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 19dba2b was da02e69, checked in by Jakub Jermar <jakub@…>, 19 years ago

Unfortunatelly, the sparc64's FPRS register is writable by non-privileged software
so we cannot save only half of the FPU context depending on FPRS dirty bits.
Instead, we must save the entire FPU register file.
  • Property mode set to 100644
File size: 5.0 KB
Line 
1/*
2 * Copyright (C) 2006 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup sparc64
30 * @{
31 */
32/** @file
33 *
34 */
35
36#include <fpu_context.h>
37#include <arch/register.h>
38#include <arch/asm.h>
39
40void fpu_context_save(fpu_context_t *fctx)
41{
42 __asm__ volatile (
43 "std %%f0, %0\n"
44 "std %%f2, %1\n"
45 "std %%f4, %2\n"
46 "std %%f6, %3\n"
47 "std %%f8, %4\n"
48 "std %%f10, %5\n"
49 "std %%f12, %6\n"
50 "std %%f14, %7\n"
51 "std %%f16, %8\n"
52 "std %%f18, %9\n"
53 "std %%f20, %10\n"
54 "std %%f22, %11\n"
55 "std %%f24, %12\n"
56 "std %%f26, %13\n"
57 "std %%f28, %14\n"
58 "std %%f30, %15\n"
59 : "=m" (fctx->d[0]), "=m" (fctx->d[1]), "=m" (fctx->d[2]), "=m" (fctx->d[3]),
60 "=m" (fctx->d[4]), "=m" (fctx->d[5]), "=m" (fctx->d[6]), "=m" (fctx->d[7]),
61 "=m" (fctx->d[8]), "=m" (fctx->d[9]), "=m" (fctx->d[10]), "=m" (fctx->d[11]),
62 "=m" (fctx->d[12]), "=m" (fctx->d[13]), "=m" (fctx->d[14]), "=m" (fctx->d[15])
63 );
64
65 /*
66 * We need to split loading of the floating-point registers because
67 * GCC (4.1.1) can't handle more than 30 operands in one asm statement.
68 */
69
70 __asm__ volatile (
71 "std %%f32, %0\n"
72 "std %%f34, %1\n"
73 "std %%f36, %2\n"
74 "std %%f38, %3\n"
75 "std %%f40, %4\n"
76 "std %%f42, %5\n"
77 "std %%f44, %6\n"
78 "std %%f46, %7\n"
79 "std %%f48, %8\n"
80 "std %%f50, %9\n"
81 "std %%f52, %10\n"
82 "std %%f54, %11\n"
83 "std %%f56, %12\n"
84 "std %%f58, %13\n"
85 "std %%f60, %14\n"
86 "std %%f62, %15\n"
87 : "=m" (fctx->d[16]), "=m" (fctx->d[17]), "=m" (fctx->d[18]), "=m" (fctx->d[19]),
88 "=m" (fctx->d[20]), "=m" (fctx->d[21]), "=m" (fctx->d[22]), "=m" (fctx->d[23]),
89 "=m" (fctx->d[24]), "=m" (fctx->d[25]), "=m" (fctx->d[26]), "=m" (fctx->d[27]),
90 "=m" (fctx->d[28]), "=m" (fctx->d[29]), "=m" (fctx->d[30]), "=m" (fctx->d[31])
91 );
92
93 __asm__ volatile ("stx %%fsr, %0\n" : "=m" (fctx->fsr));
94}
95
96void fpu_context_restore(fpu_context_t *fctx)
97{
98 __asm__ volatile (
99 "ldd %0, %%f0\n"
100 "ldd %1, %%f2\n"
101 "ldd %2, %%f4\n"
102 "ldd %3, %%f6\n"
103 "ldd %4, %%f8\n"
104 "ldd %5, %%f10\n"
105 "ldd %6, %%f12\n"
106 "ldd %7, %%f14\n"
107 "ldd %8, %%f16\n"
108 "ldd %9, %%f18\n"
109 "ldd %10, %%f20\n"
110 "ldd %11, %%f22\n"
111 "ldd %12, %%f24\n"
112 "ldd %13, %%f26\n"
113 "ldd %14, %%f28\n"
114 "ldd %15, %%f30\n"
115 :
116 : "m" (fctx->d[0]), "m" (fctx->d[1]), "m" (fctx->d[2]), "m" (fctx->d[3]),
117 "m" (fctx->d[4]), "m" (fctx->d[5]), "m" (fctx->d[6]), "m" (fctx->d[7]),
118 "m" (fctx->d[8]), "m" (fctx->d[9]), "m" (fctx->d[10]), "m" (fctx->d[11]),
119 "m" (fctx->d[12]), "m" (fctx->d[13]), "m" (fctx->d[14]), "m" (fctx->d[15])
120 );
121
122 /*
123 * We need to split loading of the floating-point registers because
124 * GCC (4.1.1) can't handle more than 30 operands in one asm statement.
125 */
126
127 __asm__ volatile (
128 "ldd %0, %%f32\n"
129 "ldd %1, %%f34\n"
130 "ldd %2, %%f36\n"
131 "ldd %3, %%f38\n"
132 "ldd %4, %%f40\n"
133 "ldd %5, %%f42\n"
134 "ldd %6, %%f44\n"
135 "ldd %7, %%f46\n"
136 "ldd %8, %%f48\n"
137 "ldd %9, %%f50\n"
138 "ldd %10, %%f52\n"
139 "ldd %11, %%f54\n"
140 "ldd %12, %%f56\n"
141 "ldd %13, %%f58\n"
142 "ldd %14, %%f60\n"
143 "ldd %15, %%f62\n"
144 :
145 : "m" (fctx->d[16]), "m" (fctx->d[17]), "m" (fctx->d[18]), "m" (fctx->d[19]),
146 "m" (fctx->d[20]), "m" (fctx->d[21]), "m" (fctx->d[22]), "m" (fctx->d[23]),
147 "m" (fctx->d[24]), "m" (fctx->d[25]), "m" (fctx->d[26]), "m" (fctx->d[27]),
148 "m" (fctx->d[28]), "m" (fctx->d[29]), "m" (fctx->d[30]), "m" (fctx->d[31])
149 );
150
151 __asm__ volatile ("ldx %0, %%fsr\n" : : "m" (fctx->fsr));
152}
153
154void fpu_enable(void)
155{
156 pstate_reg_t pstate;
157
158 pstate.value = pstate_read();
159 pstate.pef = true;
160 pstate_write(pstate.value);
161}
162
163void fpu_disable(void)
164{
165 pstate_reg_t pstate;
166
167 pstate.value = pstate_read();
168 pstate.pef = false;
169 pstate_write(pstate.value);
170}
171
172void fpu_init(void)
173{
174 fpu_enable();
175}
176
177/** @}
178 */
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