source: mainline/kernel/arch/sparc64/src/drivers/tick.c@ cefb126

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since cefb126 was d46f5cc, checked in by Martin Decky <martin@…>, 15 years ago

fix exception handler prototype

  • Property mode set to 100644
File size: 3.7 KB
Line 
1/*
2 * Copyright (c) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup sparc64
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/drivers/tick.h>
36#include <arch/interrupt.h>
37#include <arch/sparc64.h>
38#include <arch/asm.h>
39#include <arch/register.h>
40#include <arch/cpu.h>
41#include <arch/boot/boot.h>
42#include <time/clock.h>
43#include <arch.h>
44#include <debug.h>
45
46#define TICK_RESTART_TIME 50 /* Worst case estimate. */
47
48/** Initialize tick and stick interrupt. */
49void tick_init(void)
50{
51 /* initialize TICK interrupt */
52 tick_compare_reg_t compare;
53
54 interrupt_register(14, "tick_int", tick_interrupt);
55 compare.int_dis = false;
56 compare.tick_cmpr = tick_counter_read() +
57 CPU->arch.clock_frequency / HZ;
58 CPU->arch.next_tick_cmpr = compare.tick_cmpr;
59 tick_compare_write(compare.value);
60
61#if defined (US3) || defined (SUN4V)
62 /* disable STICK interrupts and clear any pending ones */
63 tick_compare_reg_t stick_compare;
64 softint_reg_t clear;
65
66 stick_compare.value = stick_compare_read();
67 stick_compare.int_dis = true;
68 stick_compare.tick_cmpr = 0;
69 stick_compare_write(stick_compare.value);
70
71 clear.value = 0;
72 clear.stick_int = 1;
73 clear_softint_write(clear.value);
74#endif
75}
76
77/** Process tick interrupt.
78 *
79 * @param n Interrupt Level (14, can be ignored)
80 * @param istate Interrupted state.
81 *
82 */
83void tick_interrupt(unsigned int n, istate_t *istate)
84{
85 softint_reg_t softint, clear;
86 uint64_t drift;
87
88 softint.value = softint_read();
89
90 /*
91 * Make sure we are servicing interrupt_level_14
92 */
93 ASSERT(n == 14);
94
95 /*
96 * Make sure we are servicing TICK_INT.
97 */
98 ASSERT(softint.tick_int);
99
100 /*
101 * Clear tick interrupt.
102 */
103 clear.value = 0;
104 clear.tick_int = 1;
105 clear_softint_write(clear.value);
106
107 /*
108 * Reprogram the compare register.
109 * For now, we can ignore the potential of the registers to overflow.
110 * On a 360MHz Ultra 60, the 63-bit compare counter will overflow in
111 * about 812 years. If there was a 2GHz UltraSPARC computer, it would
112 * overflow only in 146 years.
113 */
114 drift = tick_counter_read() - CPU->arch.next_tick_cmpr;
115 while (drift > CPU->arch.clock_frequency / HZ) {
116 drift -= CPU->arch.clock_frequency / HZ;
117 CPU->missed_clock_ticks++;
118 }
119 CPU->arch.next_tick_cmpr = tick_counter_read() +
120 (CPU->arch.clock_frequency / HZ) - drift;
121 tick_compare_write(CPU->arch.next_tick_cmpr);
122 clock();
123}
124
125/** @}
126 */
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