source:
mainline/kernel/arch/sparc64/include@
dfe9e2c
| Name | Size | Rev | Age | Author | Last Change |
|---|---|---|---|---|---|
| ../ | |||||
| trap | f2ea5d8 | 19 years | sparc64 code to support physical memory that starts on non-zero … | ||
| proc | ed166f7 | 19 years | A lot of untested sparc64 stuff: - Write ASID to hardware when a … | ||
| mm | 730376d | 19 years | Fix important comment in kernel/arch/sparc64/src/proc/scheduler.c. … | ||
| drivers | d4f184f | 19 years | sparc64 work: - untested support for Psycho PCI controller | ||
| boot | f2ea5d8 | 19 years | sparc64 code to support physical memory that starts on non-zero … | ||
| types.h | 2.0 KB | ed166f7 | 19 years | A lot of untested sparc64 stuff: - Write ASID to hardware when a … | |
| syscall.h | 1.7 KB | 9314ee1 | 19 years | sparc64 work. Kernel syscall support. Modify the preemptive_handler … | |
| stack.h | 1.9 KB | 11675207 | 17 years | Move everything to kernel/. | |
| register.h | 4.1 KB | 45b26dad | 19 years | sparc64 work: - Loader now starts all processors. - Kernel halts all … | |
| regdef.h | 2.1 KB | a9ac978 | 19 years | SMP stuff for sparc64. Almost complete except for IPIs. The absence of … | |
| memstr.h | 1.8 KB | ed166f7 | 19 years | A lot of untested sparc64 stuff: - Write ASID to hardware when a … | |
| interrupt.h | 2.3 KB | f8ddd17 | 19 years | Rework support for virtually indexed cache. Instead of repeatedly … | |
| fpu_context.h | 1.7 KB | 6eabb6e6 | 19 years | Support for sparc64 FPU context. | |
| faddr.h | 1.6 KB | ed166f7 | 19 years | A lot of untested sparc64 stuff: - Write ASID to hardware when a … | |
| elf.h | 1.7 KB | ed166f7 | 19 years | A lot of untested sparc64 stuff: - Write ASID to hardware when a … | |
| debug.h | 1.5 KB | ed166f7 | 19 years | A lot of untested sparc64 stuff: - Write ASID to hardware when a … | |
| cycle.h | 1.6 KB | 2a0cda72 | 19 years | On sparc64's tick interrupt, adjust the TICK_COMPARE register instead … | |
| cpu.h | 2.2 KB | 9a8baed | 19 years | Another comment fix. | |
| context_offset.h | 2.0 KB | f0f05ad | 19 years | sparc64 context does not have to include the CLEANWIN register. | |
| context.h | 2.3 KB | 00bb6965 | 19 years | Coding style fixes. | |
| console.h | 1.6 KB | ed166f7 | 19 years | A lot of untested sparc64 stuff: - Write ASID to hardware when a … | |
| byteorder.h | 1.8 KB | b84ce45 | 19 years | Fix mismatched byteswapping macros on sparc64. | |
| barrier.h | 2.7 KB | 1ecdbb0 | 19 years | Convert sparc64 critical section barriers to RMO memory model. More … | |
| atomic.h | 3.3 KB | a9ac978 | 19 years | SMP stuff for sparc64. Almost complete except for IPIs. The absence of … | |
| asm.h | 8.3 KB | e2cc9a0 | 19 years | Add support for interrupt mapping in the Sabre PCI controller. Add … | |
| arg.h | 1.6 KB | ed166f7 | 19 years | A lot of untested sparc64 stuff: - Write ASID to hardware when a … | |
| arch.h | 2.0 KB | 3d76996 | 19 years | Add dcache_flush() function that flushes D-Cache on sparc64. | |
|
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