source: mainline/kernel/arch/sparc64/include/trap/regwin.h@ fd85ae5

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since fd85ae5 was ed166f7, checked in by Jakub Jermar <jakub@…>, 19 years ago

A lot of untested sparc64 stuff:

  • Write ASID to hardware when a thread is about to run in userspace.
  • Add userspace() and switch_to_userspace() functions.
  • Handle special cases when the userspace spill/fill handler causes MMU trap.
  • Resolve some TODOs in the existing sparc64 code.
  • sparc64 has now C99 compliant header guards.
  • Formatting and indentation fixes.
  • Property mode set to 100644
File size: 7.0 KB
Line 
1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup sparc64interrupt
30 * @{
31 */
32/**
33 * @file
34 * @brief This file contains register window trap handlers.
35 */
36
37#ifndef KERN_sparc64_REGWIN_H_
38#define KERN_sparc64_REGWIN_H_
39
40#include <arch/stack.h>
41#include <arch/arch.h>
42
43#define TT_CLEAN_WINDOW 0x24
44#define TT_SPILL_0_NORMAL 0x80 /* kernel spills */
45#define TT_SPILL_1_NORMAL 0x84 /* userspace spills */
46#define TT_SPILL_2_NORMAL 0x88 /* spills to userspace window buffer */
47#define TT_SPILL_0_OTHER 0xa0 /* spills to userspace window buffer */
48#define TT_FILL_0_NORMAL 0xc0 /* kernel fills */
49#define TT_FILL_1_NORMAL 0xc4 /* userspace fills */
50
51#define REGWIN_HANDLER_SIZE 128
52
53#define CLEAN_WINDOW_HANDLER_SIZE REGWIN_HANDLER_SIZE
54#define SPILL_HANDLER_SIZE REGWIN_HANDLER_SIZE
55#define FILL_HANDLER_SIZE REGWIN_HANDLER_SIZE
56
57/* Window Save Area offsets. */
58#define L0_OFFSET 0
59#define L1_OFFSET 8
60#define L2_OFFSET 16
61#define L3_OFFSET 24
62#define L4_OFFSET 32
63#define L5_OFFSET 40
64#define L6_OFFSET 48
65#define L7_OFFSET 56
66#define I0_OFFSET 64
67#define I1_OFFSET 72
68#define I2_OFFSET 80
69#define I3_OFFSET 88
70#define I4_OFFSET 96
71#define I5_OFFSET 104
72#define I6_OFFSET 112
73#define I7_OFFSET 120
74
75#ifdef __ASM__
76
77/*
78 * Macro used by the nucleus and the primary context 0 during normal and other spills.
79 */
80.macro SPILL_NORMAL_HANDLER_KERNEL
81 stx %l0, [%sp + STACK_BIAS + L0_OFFSET]
82 stx %l1, [%sp + STACK_BIAS + L1_OFFSET]
83 stx %l2, [%sp + STACK_BIAS + L2_OFFSET]
84 stx %l3, [%sp + STACK_BIAS + L3_OFFSET]
85 stx %l4, [%sp + STACK_BIAS + L4_OFFSET]
86 stx %l5, [%sp + STACK_BIAS + L5_OFFSET]
87 stx %l6, [%sp + STACK_BIAS + L6_OFFSET]
88 stx %l7, [%sp + STACK_BIAS + L7_OFFSET]
89 stx %i0, [%sp + STACK_BIAS + I0_OFFSET]
90 stx %i1, [%sp + STACK_BIAS + I1_OFFSET]
91 stx %i2, [%sp + STACK_BIAS + I2_OFFSET]
92 stx %i3, [%sp + STACK_BIAS + I3_OFFSET]
93 stx %i4, [%sp + STACK_BIAS + I4_OFFSET]
94 stx %i5, [%sp + STACK_BIAS + I5_OFFSET]
95 stx %i6, [%sp + STACK_BIAS + I6_OFFSET]
96 stx %i7, [%sp + STACK_BIAS + I7_OFFSET]
97 saved
98 retry
99.endm
100
101/*
102 * Macro used by the userspace during normal spills.
103 */
104.macro SPILL_NORMAL_HANDLER_USERSPACE
105 wr %g0, ASI_AIUP, %asi
106 stxa %l0, [%sp + STACK_BIAS + L0_OFFSET] %asi
107 stxa %l1, [%sp + STACK_BIAS + L1_OFFSET] %asi
108 stxa %l2, [%sp + STACK_BIAS + L2_OFFSET] %asi
109 stxa %l3, [%sp + STACK_BIAS + L3_OFFSET] %asi
110 stxa %l4, [%sp + STACK_BIAS + L4_OFFSET] %asi
111 stxa %l5, [%sp + STACK_BIAS + L5_OFFSET] %asi
112 stxa %l6, [%sp + STACK_BIAS + L6_OFFSET] %asi
113 stxa %l7, [%sp + STACK_BIAS + L7_OFFSET] %asi
114 stxa %i0, [%sp + STACK_BIAS + I0_OFFSET] %asi
115 stxa %i1, [%sp + STACK_BIAS + I1_OFFSET] %asi
116 stxa %i2, [%sp + STACK_BIAS + I2_OFFSET] %asi
117 stxa %i3, [%sp + STACK_BIAS + I3_OFFSET] %asi
118 stxa %i4, [%sp + STACK_BIAS + I4_OFFSET] %asi
119 stxa %i5, [%sp + STACK_BIAS + I5_OFFSET] %asi
120 stxa %i6, [%sp + STACK_BIAS + I6_OFFSET] %asi
121 stxa %i7, [%sp + STACK_BIAS + I7_OFFSET] %asi
122 saved
123 retry
124.endm
125
126/*
127 * Macro used to spill userspace window to userspace window buffer.
128 * It can be either triggered from preemptible_handler doing SAVE
129 * at (TL=1) or from normal kernel code doing SAVE when OTHERWIN>0
130 * at (TL=0).
131 */
132.macro SPILL_TO_USPACE_WINDOW_BUFFER
133 stx %l0, [%g7 + L0_OFFSET]
134 stx %l1, [%g7 + L1_OFFSET]
135 stx %l2, [%g7 + L2_OFFSET]
136 stx %l3, [%g7 + L3_OFFSET]
137 stx %l4, [%g7 + L4_OFFSET]
138 stx %l5, [%g7 + L5_OFFSET]
139 stx %l6, [%g7 + L6_OFFSET]
140 stx %l7, [%g7 + L7_OFFSET]
141 stx %i0, [%g7 + I0_OFFSET]
142 stx %i1, [%g7 + I1_OFFSET]
143 stx %i2, [%g7 + I2_OFFSET]
144 stx %i3, [%g7 + I3_OFFSET]
145 stx %i4, [%g7 + I4_OFFSET]
146 stx %i5, [%g7 + I5_OFFSET]
147 stx %i6, [%g7 + I6_OFFSET]
148 stx %i7, [%g7 + I7_OFFSET]
149 add %g7, STACK_WINDOW_SAVE_AREA_SIZE, %g7
150 saved
151 retry
152.endm
153
154
155/*
156 * Macro used by the nucleus and the primary context 0 during normal fills.
157 */
158.macro FILL_NORMAL_HANDLER_KERNEL
159 ldx [%sp + STACK_BIAS + L0_OFFSET], %l0
160 ldx [%sp + STACK_BIAS + L1_OFFSET], %l1
161 ldx [%sp + STACK_BIAS + L2_OFFSET], %l2
162 ldx [%sp + STACK_BIAS + L3_OFFSET], %l3
163 ldx [%sp + STACK_BIAS + L4_OFFSET], %l4
164 ldx [%sp + STACK_BIAS + L5_OFFSET], %l5
165 ldx [%sp + STACK_BIAS + L6_OFFSET], %l6
166 ldx [%sp + STACK_BIAS + L7_OFFSET], %l7
167 ldx [%sp + STACK_BIAS + I0_OFFSET], %i0
168 ldx [%sp + STACK_BIAS + I1_OFFSET], %i1
169 ldx [%sp + STACK_BIAS + I2_OFFSET], %i2
170 ldx [%sp + STACK_BIAS + I3_OFFSET], %i3
171 ldx [%sp + STACK_BIAS + I4_OFFSET], %i4
172 ldx [%sp + STACK_BIAS + I5_OFFSET], %i5
173 ldx [%sp + STACK_BIAS + I6_OFFSET], %i6
174 ldx [%sp + STACK_BIAS + I7_OFFSET], %i7
175 restored
176 retry
177.endm
178
179/*
180 * Macro used by the userspace during normal fills.
181 */
182.macro FILL_NORMAL_HANDLER_USERSPACE
183 wr %g0, ASI_AIUP, %asi
184 ldxa [%sp + STACK_BIAS + L0_OFFSET] %asi, %l0
185 ldxa [%sp + STACK_BIAS + L1_OFFSET] %asi, %l1
186 ldxa [%sp + STACK_BIAS + L2_OFFSET] %asi, %l2
187 ldxa [%sp + STACK_BIAS + L3_OFFSET] %asi, %l3
188 ldxa [%sp + STACK_BIAS + L4_OFFSET] %asi, %l4
189 ldxa [%sp + STACK_BIAS + L5_OFFSET] %asi, %l5
190 ldxa [%sp + STACK_BIAS + L6_OFFSET] %asi, %l6
191 ldxa [%sp + STACK_BIAS + L7_OFFSET] %asi, %l7
192 ldxa [%sp + STACK_BIAS + I0_OFFSET] %asi, %i0
193 ldxa [%sp + STACK_BIAS + I1_OFFSET] %asi, %i1
194 ldxa [%sp + STACK_BIAS + I2_OFFSET] %asi, %i2
195 ldxa [%sp + STACK_BIAS + I3_OFFSET] %asi, %i3
196 ldxa [%sp + STACK_BIAS + I4_OFFSET] %asi, %i4
197 ldxa [%sp + STACK_BIAS + I5_OFFSET] %asi, %i5
198 ldxa [%sp + STACK_BIAS + I6_OFFSET] %asi, %i6
199 ldxa [%sp + STACK_BIAS + I7_OFFSET] %asi, %i7
200 restored
201 retry
202.endm
203
204.macro CLEAN_WINDOW_HANDLER
205 rdpr %cleanwin, %l0
206 add %l0, 1, %l0
207 wrpr %l0, 0, %cleanwin
208 mov %r0, %l0
209 mov %r0, %l1
210 mov %r0, %l2
211 mov %r0, %l3
212 mov %r0, %l4
213 mov %r0, %l5
214 mov %r0, %l6
215 mov %r0, %l7
216 mov %r0, %o0
217 mov %r0, %o1
218 mov %r0, %o2
219 mov %r0, %o3
220 mov %r0, %o4
221 mov %r0, %o5
222 mov %r0, %o6
223 mov %r0, %o7
224 retry
225.endm
226#endif /* __ASM__ */
227
228#endif
229
230/** @}
231 */
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