source: mainline/kernel/arch/sparc64/include/trap/regwin.h@ 86018c1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 86018c1 was eb79d60, checked in by Pavel Rimsky <pavel@…>, 16 years ago

Merged the preemptible trap handler for userspace.
  • Property mode set to 100644
File size: 6.6 KB
Line 
1/*
2 * Copyright (c) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup sparc64interrupt
30 * @{
31 */
32/**
33 * @file
34 * @brief This file contains register window trap handlers.
35 */
36
37#ifndef KERN_sparc64_REGWIN_H_
38#define KERN_sparc64_REGWIN_H_
39
40#include <arch/stack.h>
41#include <arch/arch.h>
42#include <align.h>
43
44#define TT_CLEAN_WINDOW 0x24
45#define TT_SPILL_0_NORMAL 0x80 /* kernel spills */
46#define TT_SPILL_1_NORMAL 0x84 /* userspace spills */
47#define TT_SPILL_2_NORMAL 0x88 /* spills to userspace window buffer */
48#define TT_SPILL_0_OTHER 0xa0 /* spills to userspace window buffer */
49#define TT_FILL_0_NORMAL 0xc0 /* kernel fills */
50#define TT_FILL_1_NORMAL 0xc4 /* userspace fills */
51
52#define REGWIN_HANDLER_SIZE 128
53
54#define CLEAN_WINDOW_HANDLER_SIZE REGWIN_HANDLER_SIZE
55#define SPILL_HANDLER_SIZE REGWIN_HANDLER_SIZE
56#define FILL_HANDLER_SIZE REGWIN_HANDLER_SIZE
57
58/* Window Save Area offsets. */
59#define L0_OFFSET 0
60#define L1_OFFSET 8
61#define L2_OFFSET 16
62#define L3_OFFSET 24
63#define L4_OFFSET 32
64#define L5_OFFSET 40
65#define L6_OFFSET 48
66#define L7_OFFSET 56
67#define I0_OFFSET 64
68#define I1_OFFSET 72
69#define I2_OFFSET 80
70#define I3_OFFSET 88
71#define I4_OFFSET 96
72#define I5_OFFSET 104
73#define I6_OFFSET 112
74#define I7_OFFSET 120
75
76/* Uspace Window Buffer constants. */
77#define UWB_SIZE ((NWINDOWS - 1) * STACK_WINDOW_SAVE_AREA_SIZE)
78#define UWB_ALIGNMENT 1024
79#define UWB_ASIZE ALIGN_UP(UWB_SIZE, UWB_ALIGNMENT)
80
81#ifdef __ASM__
82
83/*
84 * Macro used by the nucleus and the primary context 0 during normal and other spills.
85 */
86.macro SPILL_NORMAL_HANDLER_KERNEL
87 stx %l0, [%sp + STACK_BIAS + L0_OFFSET]
88 stx %l1, [%sp + STACK_BIAS + L1_OFFSET]
89 stx %l2, [%sp + STACK_BIAS + L2_OFFSET]
90 stx %l3, [%sp + STACK_BIAS + L3_OFFSET]
91 stx %l4, [%sp + STACK_BIAS + L4_OFFSET]
92 stx %l5, [%sp + STACK_BIAS + L5_OFFSET]
93 stx %l6, [%sp + STACK_BIAS + L6_OFFSET]
94 stx %l7, [%sp + STACK_BIAS + L7_OFFSET]
95 stx %i0, [%sp + STACK_BIAS + I0_OFFSET]
96 stx %i1, [%sp + STACK_BIAS + I1_OFFSET]
97 stx %i2, [%sp + STACK_BIAS + I2_OFFSET]
98 stx %i3, [%sp + STACK_BIAS + I3_OFFSET]
99 stx %i4, [%sp + STACK_BIAS + I4_OFFSET]
100 stx %i5, [%sp + STACK_BIAS + I5_OFFSET]
101 stx %i6, [%sp + STACK_BIAS + I6_OFFSET]
102 stx %i7, [%sp + STACK_BIAS + I7_OFFSET]
103 saved
104 retry
105.endm
106
107/*
108 * Macro used by the userspace during normal spills.
109 */
110.macro SPILL_NORMAL_HANDLER_USERSPACE
111 wr %g0, ASI_AIUP, %asi
112 stxa %l0, [%sp + STACK_BIAS + L0_OFFSET] %asi
113 stxa %l1, [%sp + STACK_BIAS + L1_OFFSET] %asi
114 stxa %l2, [%sp + STACK_BIAS + L2_OFFSET] %asi
115 stxa %l3, [%sp + STACK_BIAS + L3_OFFSET] %asi
116 stxa %l4, [%sp + STACK_BIAS + L4_OFFSET] %asi
117 stxa %l5, [%sp + STACK_BIAS + L5_OFFSET] %asi
118 stxa %l6, [%sp + STACK_BIAS + L6_OFFSET] %asi
119 stxa %l7, [%sp + STACK_BIAS + L7_OFFSET] %asi
120 stxa %i0, [%sp + STACK_BIAS + I0_OFFSET] %asi
121 stxa %i1, [%sp + STACK_BIAS + I1_OFFSET] %asi
122 stxa %i2, [%sp + STACK_BIAS + I2_OFFSET] %asi
123 stxa %i3, [%sp + STACK_BIAS + I3_OFFSET] %asi
124 stxa %i4, [%sp + STACK_BIAS + I4_OFFSET] %asi
125 stxa %i5, [%sp + STACK_BIAS + I5_OFFSET] %asi
126 stxa %i6, [%sp + STACK_BIAS + I6_OFFSET] %asi
127 stxa %i7, [%sp + STACK_BIAS + I7_OFFSET] %asi
128 saved
129 retry
130.endm
131
132/*
133 * Macro used by the nucleus and the primary context 0 during normal fills.
134 */
135.macro FILL_NORMAL_HANDLER_KERNEL
136 ldx [%sp + STACK_BIAS + L0_OFFSET], %l0
137 ldx [%sp + STACK_BIAS + L1_OFFSET], %l1
138 ldx [%sp + STACK_BIAS + L2_OFFSET], %l2
139 ldx [%sp + STACK_BIAS + L3_OFFSET], %l3
140 ldx [%sp + STACK_BIAS + L4_OFFSET], %l4
141 ldx [%sp + STACK_BIAS + L5_OFFSET], %l5
142 ldx [%sp + STACK_BIAS + L6_OFFSET], %l6
143 ldx [%sp + STACK_BIAS + L7_OFFSET], %l7
144 ldx [%sp + STACK_BIAS + I0_OFFSET], %i0
145 ldx [%sp + STACK_BIAS + I1_OFFSET], %i1
146 ldx [%sp + STACK_BIAS + I2_OFFSET], %i2
147 ldx [%sp + STACK_BIAS + I3_OFFSET], %i3
148 ldx [%sp + STACK_BIAS + I4_OFFSET], %i4
149 ldx [%sp + STACK_BIAS + I5_OFFSET], %i5
150 ldx [%sp + STACK_BIAS + I6_OFFSET], %i6
151 ldx [%sp + STACK_BIAS + I7_OFFSET], %i7
152 restored
153 retry
154.endm
155
156/*
157 * Macro used by the userspace during normal fills.
158 */
159.macro FILL_NORMAL_HANDLER_USERSPACE
160 wr %g0, ASI_AIUP, %asi
161 ldxa [%sp + STACK_BIAS + L0_OFFSET] %asi, %l0
162 ldxa [%sp + STACK_BIAS + L1_OFFSET] %asi, %l1
163 ldxa [%sp + STACK_BIAS + L2_OFFSET] %asi, %l2
164 ldxa [%sp + STACK_BIAS + L3_OFFSET] %asi, %l3
165 ldxa [%sp + STACK_BIAS + L4_OFFSET] %asi, %l4
166 ldxa [%sp + STACK_BIAS + L5_OFFSET] %asi, %l5
167 ldxa [%sp + STACK_BIAS + L6_OFFSET] %asi, %l6
168 ldxa [%sp + STACK_BIAS + L7_OFFSET] %asi, %l7
169 ldxa [%sp + STACK_BIAS + I0_OFFSET] %asi, %i0
170 ldxa [%sp + STACK_BIAS + I1_OFFSET] %asi, %i1
171 ldxa [%sp + STACK_BIAS + I2_OFFSET] %asi, %i2
172 ldxa [%sp + STACK_BIAS + I3_OFFSET] %asi, %i3
173 ldxa [%sp + STACK_BIAS + I4_OFFSET] %asi, %i4
174 ldxa [%sp + STACK_BIAS + I5_OFFSET] %asi, %i5
175 ldxa [%sp + STACK_BIAS + I6_OFFSET] %asi, %i6
176 ldxa [%sp + STACK_BIAS + I7_OFFSET] %asi, %i7
177 restored
178 retry
179.endm
180
181.macro CLEAN_WINDOW_HANDLER
182 rdpr %cleanwin, %l0
183 add %l0, 1, %l0
184 wrpr %l0, 0, %cleanwin
185 mov %r0, %l0
186 mov %r0, %l1
187 mov %r0, %l2
188 mov %r0, %l3
189 mov %r0, %l4
190 mov %r0, %l5
191 mov %r0, %l6
192 mov %r0, %l7
193 mov %r0, %o0
194 mov %r0, %o1
195 mov %r0, %o2
196 mov %r0, %o3
197 mov %r0, %o4
198 mov %r0, %o5
199 mov %r0, %o6
200 mov %r0, %o7
201 retry
202.endm
203#endif /* __ASM__ */
204
205#if defined (SUN4U)
206#include <arch/trap/sun4u/regwin.h>
207#elif defined (SUN4V)
208#include <arch/trap/sun4v/regwin.h>
209#endif
210
211#endif
212
213/** @}
214 */
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