| [49b6d32] | 1 | /*
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| [df4ed85] | 2 | * Copyright (c) 2005 Jakub Jermar
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| [49b6d32] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| [3222efd] | 29 | /** @addtogroup sparc64interrupt
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| [b45c443] | 30 | * @{
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| 31 | */
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| [49b6d32] | 32 | /**
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| [3222efd] | 33 | * @file
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| 34 | * @brief This file contains register window trap handlers.
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| [49b6d32] | 35 | */
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| 36 |
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| [ed166f7] | 37 | #ifndef KERN_sparc64_REGWIN_H_
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| 38 | #define KERN_sparc64_REGWIN_H_
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| [49b6d32] | 39 |
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| 40 | #include <arch/stack.h>
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| [a7961271] | 41 | #include <arch/arch.h>
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| [d364e94] | 42 | #include <align.h>
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| [49b6d32] | 43 |
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| 44 | #define TT_CLEAN_WINDOW 0x24
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| [e11ae91] | 45 | #define TT_SPILL_0_NORMAL 0x80 /* kernel spills */
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| 46 | #define TT_SPILL_1_NORMAL 0x84 /* userspace spills */
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| 47 | #define TT_SPILL_2_NORMAL 0x88 /* spills to userspace window buffer */
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| 48 | #define TT_SPILL_0_OTHER 0xa0 /* spills to userspace window buffer */
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| 49 | #define TT_FILL_0_NORMAL 0xc0 /* kernel fills */
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| 50 | #define TT_FILL_1_NORMAL 0xc4 /* userspace fills */
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| [49b6d32] | 51 |
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| 52 | #define REGWIN_HANDLER_SIZE 128
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| 53 |
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| 54 | #define CLEAN_WINDOW_HANDLER_SIZE REGWIN_HANDLER_SIZE
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| 55 | #define SPILL_HANDLER_SIZE REGWIN_HANDLER_SIZE
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| 56 | #define FILL_HANDLER_SIZE REGWIN_HANDLER_SIZE
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| 57 |
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| [a7961271] | 58 | /* Window Save Area offsets. */
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| [49b6d32] | 59 | #define L0_OFFSET 0
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| 60 | #define L1_OFFSET 8
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| 61 | #define L2_OFFSET 16
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| 62 | #define L3_OFFSET 24
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| 63 | #define L4_OFFSET 32
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| 64 | #define L5_OFFSET 40
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| 65 | #define L6_OFFSET 48
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| 66 | #define L7_OFFSET 56
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| 67 | #define I0_OFFSET 64
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| 68 | #define I1_OFFSET 72
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| 69 | #define I2_OFFSET 80
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| 70 | #define I3_OFFSET 88
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| 71 | #define I4_OFFSET 96
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| 72 | #define I5_OFFSET 104
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| 73 | #define I6_OFFSET 112
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| 74 | #define I7_OFFSET 120
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| 75 |
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| [d364e94] | 76 | /* Uspace Window Buffer constants. */
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| 77 | #define UWB_SIZE ((NWINDOWS - 1) * STACK_WINDOW_SAVE_AREA_SIZE)
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| 78 | #define UWB_ALIGNMENT 1024
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| 79 | #define UWB_ASIZE ALIGN_UP(UWB_SIZE, UWB_ALIGNMENT)
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| 80 |
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| [cddc1639] | 81 | #ifdef __ASM__
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| [a7961271] | 82 |
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| 83 | /*
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| 84 | * Macro used by the nucleus and the primary context 0 during normal and other spills.
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| 85 | */
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| 86 | .macro SPILL_NORMAL_HANDLER_KERNEL
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| [49b6d32] | 87 | stx %l0, [%sp + STACK_BIAS + L0_OFFSET]
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| 88 | stx %l1, [%sp + STACK_BIAS + L1_OFFSET]
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| 89 | stx %l2, [%sp + STACK_BIAS + L2_OFFSET]
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| 90 | stx %l3, [%sp + STACK_BIAS + L3_OFFSET]
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| 91 | stx %l4, [%sp + STACK_BIAS + L4_OFFSET]
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| 92 | stx %l5, [%sp + STACK_BIAS + L5_OFFSET]
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| 93 | stx %l6, [%sp + STACK_BIAS + L6_OFFSET]
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| 94 | stx %l7, [%sp + STACK_BIAS + L7_OFFSET]
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| 95 | stx %i0, [%sp + STACK_BIAS + I0_OFFSET]
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| 96 | stx %i1, [%sp + STACK_BIAS + I1_OFFSET]
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| 97 | stx %i2, [%sp + STACK_BIAS + I2_OFFSET]
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| 98 | stx %i3, [%sp + STACK_BIAS + I3_OFFSET]
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| 99 | stx %i4, [%sp + STACK_BIAS + I4_OFFSET]
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| 100 | stx %i5, [%sp + STACK_BIAS + I5_OFFSET]
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| 101 | stx %i6, [%sp + STACK_BIAS + I6_OFFSET]
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| 102 | stx %i7, [%sp + STACK_BIAS + I7_OFFSET]
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| 103 | saved
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| 104 | retry
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| 105 | .endm
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| 106 |
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| [a7961271] | 107 | /*
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| 108 | * Macro used by the userspace during normal spills.
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| 109 | */
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| 110 | .macro SPILL_NORMAL_HANDLER_USERSPACE
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| [e11ae91] | 111 | wr %g0, ASI_AIUP, %asi
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| [a7961271] | 112 | stxa %l0, [%sp + STACK_BIAS + L0_OFFSET] %asi
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| 113 | stxa %l1, [%sp + STACK_BIAS + L1_OFFSET] %asi
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| 114 | stxa %l2, [%sp + STACK_BIAS + L2_OFFSET] %asi
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| 115 | stxa %l3, [%sp + STACK_BIAS + L3_OFFSET] %asi
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| 116 | stxa %l4, [%sp + STACK_BIAS + L4_OFFSET] %asi
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| 117 | stxa %l5, [%sp + STACK_BIAS + L5_OFFSET] %asi
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| 118 | stxa %l6, [%sp + STACK_BIAS + L6_OFFSET] %asi
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| 119 | stxa %l7, [%sp + STACK_BIAS + L7_OFFSET] %asi
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| 120 | stxa %i0, [%sp + STACK_BIAS + I0_OFFSET] %asi
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| 121 | stxa %i1, [%sp + STACK_BIAS + I1_OFFSET] %asi
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| 122 | stxa %i2, [%sp + STACK_BIAS + I2_OFFSET] %asi
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| 123 | stxa %i3, [%sp + STACK_BIAS + I3_OFFSET] %asi
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| 124 | stxa %i4, [%sp + STACK_BIAS + I4_OFFSET] %asi
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| 125 | stxa %i5, [%sp + STACK_BIAS + I5_OFFSET] %asi
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| 126 | stxa %i6, [%sp + STACK_BIAS + I6_OFFSET] %asi
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| 127 | stxa %i7, [%sp + STACK_BIAS + I7_OFFSET] %asi
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| 128 | saved
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| 129 | retry
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| 130 | .endm
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| 131 |
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| 132 | /*
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| 133 | * Macro used by the nucleus and the primary context 0 during normal fills.
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| 134 | */
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| 135 | .macro FILL_NORMAL_HANDLER_KERNEL
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| [49b6d32] | 136 | ldx [%sp + STACK_BIAS + L0_OFFSET], %l0
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| 137 | ldx [%sp + STACK_BIAS + L1_OFFSET], %l1
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| 138 | ldx [%sp + STACK_BIAS + L2_OFFSET], %l2
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| 139 | ldx [%sp + STACK_BIAS + L3_OFFSET], %l3
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| 140 | ldx [%sp + STACK_BIAS + L4_OFFSET], %l4
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| 141 | ldx [%sp + STACK_BIAS + L5_OFFSET], %l5
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| 142 | ldx [%sp + STACK_BIAS + L6_OFFSET], %l6
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| 143 | ldx [%sp + STACK_BIAS + L7_OFFSET], %l7
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| 144 | ldx [%sp + STACK_BIAS + I0_OFFSET], %i0
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| 145 | ldx [%sp + STACK_BIAS + I1_OFFSET], %i1
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| 146 | ldx [%sp + STACK_BIAS + I2_OFFSET], %i2
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| 147 | ldx [%sp + STACK_BIAS + I3_OFFSET], %i3
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| 148 | ldx [%sp + STACK_BIAS + I4_OFFSET], %i4
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| 149 | ldx [%sp + STACK_BIAS + I5_OFFSET], %i5
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| 150 | ldx [%sp + STACK_BIAS + I6_OFFSET], %i6
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| 151 | ldx [%sp + STACK_BIAS + I7_OFFSET], %i7
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| 152 | restored
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| 153 | retry
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| 154 | .endm
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| 155 |
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| [a7961271] | 156 | /*
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| 157 | * Macro used by the userspace during normal fills.
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| 158 | */
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| 159 | .macro FILL_NORMAL_HANDLER_USERSPACE
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| [e11ae91] | 160 | wr %g0, ASI_AIUP, %asi
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| [a7961271] | 161 | ldxa [%sp + STACK_BIAS + L0_OFFSET] %asi, %l0
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| 162 | ldxa [%sp + STACK_BIAS + L1_OFFSET] %asi, %l1
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| 163 | ldxa [%sp + STACK_BIAS + L2_OFFSET] %asi, %l2
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| 164 | ldxa [%sp + STACK_BIAS + L3_OFFSET] %asi, %l3
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| 165 | ldxa [%sp + STACK_BIAS + L4_OFFSET] %asi, %l4
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| 166 | ldxa [%sp + STACK_BIAS + L5_OFFSET] %asi, %l5
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| 167 | ldxa [%sp + STACK_BIAS + L6_OFFSET] %asi, %l6
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| 168 | ldxa [%sp + STACK_BIAS + L7_OFFSET] %asi, %l7
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| 169 | ldxa [%sp + STACK_BIAS + I0_OFFSET] %asi, %i0
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| 170 | ldxa [%sp + STACK_BIAS + I1_OFFSET] %asi, %i1
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| 171 | ldxa [%sp + STACK_BIAS + I2_OFFSET] %asi, %i2
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| 172 | ldxa [%sp + STACK_BIAS + I3_OFFSET] %asi, %i3
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| 173 | ldxa [%sp + STACK_BIAS + I4_OFFSET] %asi, %i4
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| 174 | ldxa [%sp + STACK_BIAS + I5_OFFSET] %asi, %i5
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| 175 | ldxa [%sp + STACK_BIAS + I6_OFFSET] %asi, %i6
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| 176 | ldxa [%sp + STACK_BIAS + I7_OFFSET] %asi, %i7
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| 177 | restored
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| 178 | retry
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| 179 | .endm
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| 180 |
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| [49b6d32] | 181 | .macro CLEAN_WINDOW_HANDLER
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| 182 | rdpr %cleanwin, %l0
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| 183 | add %l0, 1, %l0
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| 184 | wrpr %l0, 0, %cleanwin
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| [68acf21] | 185 | #if defined(SUN4U)
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| [49b6d32] | 186 | mov %r0, %l0
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| 187 | mov %r0, %l1
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| 188 | mov %r0, %l2
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| 189 | mov %r0, %l3
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| 190 | mov %r0, %l4
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| 191 | mov %r0, %l5
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| 192 | mov %r0, %l6
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| 193 | mov %r0, %l7
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| [7614565] | 194 | mov %r0, %o0
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| 195 | mov %r0, %o1
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| 196 | mov %r0, %o2
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| 197 | mov %r0, %o3
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| 198 | mov %r0, %o4
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| 199 | mov %r0, %o5
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| 200 | mov %r0, %o6
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| 201 | mov %r0, %o7
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| [68acf21] | 202 | #endif
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| [49b6d32] | 203 | retry
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| 204 | .endm
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| [cddc1639] | 205 | #endif /* __ASM__ */
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| [49b6d32] | 206 |
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| [68acf21] | 207 | #if defined(SUN4U)
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| [eb79d60] | 208 | #include <arch/trap/sun4u/regwin.h>
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| [68acf21] | 209 | #elif defined(SUN4V)
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| [eb79d60] | 210 | #include <arch/trap/sun4v/regwin.h>
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| 211 | #endif
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| 212 |
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| [49b6d32] | 213 | #endif
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| [b45c443] | 214 |
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| [3222efd] | 215 | /** @}
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| [b45c443] | 216 | */
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