source: mainline/kernel/arch/sparc64/include/mm/sun4u/tlb.h@ 7a0359b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 7a0359b was 7a0359b, checked in by Martin Decky <martin@…>, 15 years ago

improve kernel function tracing

  • add support for more generic kernel sources
  • replace attribute((no_instrument_function)) with NO_TRACE macro (shorter and for future compatibility with different compilers)
  • to be on the safe side, do not instrument most of the inline and static functions (plus some specific non-static functions)

collateral code cleanup (no change in functionality)
  • Property mode set to 100644
File size: 17.1 KB
Line 
1/*
2 * Copyright (c) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup sparc64mm
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_sparc64_TLB_sun4u_H_
36#define KERN_sparc64_TLB_sun4u_H_
37
38#if defined (US)
39#define ITLB_ENTRY_COUNT 64
40#define DTLB_ENTRY_COUNT 64
41#define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT
42#endif
43
44/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
45#if defined (US3)
46#define DTLB_MAX_LOCKED_ENTRIES 16
47#endif
48
49#define MEM_CONTEXT_KERNEL 0
50#define MEM_CONTEXT_TEMP 1
51
52/** Page sizes. */
53#define PAGESIZE_8K 0
54#define PAGESIZE_64K 1
55#define PAGESIZE_512K 2
56#define PAGESIZE_4M 3
57
58/** Bit width of the TLB-locked portion of kernel address space. */
59#define KERNEL_PAGE_WIDTH 22 /* 4M */
60
61/* TLB Demap Operation types. */
62#define TLB_DEMAP_PAGE 0
63#define TLB_DEMAP_CONTEXT 1
64#if defined (US3)
65#define TLB_DEMAP_ALL 2
66#endif
67
68#define TLB_DEMAP_TYPE_SHIFT 6
69
70/* TLB Demap Operation Context register encodings. */
71#define TLB_DEMAP_PRIMARY 0
72#define TLB_DEMAP_SECONDARY 1
73#define TLB_DEMAP_NUCLEUS 2
74
75/* There are more TLBs in one MMU in US3, their codes are defined here. */
76#if defined (US3)
77/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */
78#define TLB_DSMALL 0
79#define TLB_DBIG_0 2
80#define TLB_DBIG_1 3
81
82/* I-MMU: one small (16-entry) TLB and one big TLB */
83#define TLB_ISMALL 0
84#define TLB_IBIG 2
85#endif
86
87#define TLB_DEMAP_CONTEXT_SHIFT 4
88
89/* TLB Tag Access shifts */
90#define TLB_TAG_ACCESS_CONTEXT_SHIFT 0
91#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1)
92#define TLB_TAG_ACCESS_VPN_SHIFT 13
93
94#ifndef __ASM__
95
96#include <arch/mm/tte.h>
97#include <arch/mm/mmu.h>
98#include <arch/mm/page.h>
99#include <arch/asm.h>
100#include <arch/barrier.h>
101#include <typedefs.h>
102#include <trace.h>
103#include <arch/register.h>
104#include <arch/cpu.h>
105
106union tlb_context_reg {
107 uint64_t v;
108 struct {
109 unsigned long : 51;
110 unsigned context : 13; /**< Context/ASID. */
111 } __attribute__ ((packed));
112};
113typedef union tlb_context_reg tlb_context_reg_t;
114
115/** I-/D-TLB Data In/Access Register type. */
116typedef tte_data_t tlb_data_t;
117
118/** I-/D-TLB Data Access Address in Alternate Space. */
119
120#if defined (US)
121
122union tlb_data_access_addr {
123 uint64_t value;
124 struct {
125 uint64_t : 55;
126 unsigned tlb_entry : 6;
127 unsigned : 3;
128 } __attribute__ ((packed));
129};
130typedef union tlb_data_access_addr dtlb_data_access_addr_t;
131typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
132typedef union tlb_data_access_addr itlb_data_access_addr_t;
133typedef union tlb_data_access_addr itlb_tag_read_addr_t;
134
135#elif defined (US3)
136
137/*
138 * In US3, I-MMU and D-MMU have different formats of the data
139 * access register virtual address. In the corresponding
140 * structures the member variable for the entry number is
141 * called "local_tlb_entry" - it contrasts with the "tlb_entry"
142 * for the US data access register VA structure. The rationale
143 * behind this is to prevent careless mistakes in the code
144 * caused by setting only the entry number and not the TLB
145 * number in the US3 code (when taking the code from US).
146 */
147
148union dtlb_data_access_addr {
149 uint64_t value;
150 struct {
151 uint64_t : 45;
152 unsigned : 1;
153 unsigned tlb_number : 2;
154 unsigned : 4;
155 unsigned local_tlb_entry : 9;
156 unsigned : 3;
157 } __attribute__ ((packed));
158};
159typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
160typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
161
162union itlb_data_access_addr {
163 uint64_t value;
164 struct {
165 uint64_t : 45;
166 unsigned : 1;
167 unsigned tlb_number : 2;
168 unsigned : 6;
169 unsigned local_tlb_entry : 7;
170 unsigned : 3;
171 } __attribute__ ((packed));
172};
173typedef union itlb_data_access_addr itlb_data_access_addr_t;
174typedef union itlb_data_access_addr itlb_tag_read_addr_t;
175
176#endif
177
178/** I-/D-TLB Tag Read Register. */
179union tlb_tag_read_reg {
180 uint64_t value;
181 struct {
182 uint64_t vpn : 51; /**< Virtual Address bits 63:13. */
183 unsigned context : 13; /**< Context identifier. */
184 } __attribute__ ((packed));
185};
186typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
187typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
188
189
190/** TLB Demap Operation Address. */
191union tlb_demap_addr {
192 uint64_t value;
193 struct {
194 uint64_t vpn: 51; /**< Virtual Address bits 63:13. */
195#if defined (US)
196 unsigned : 6; /**< Ignored. */
197 unsigned type : 1; /**< The type of demap operation. */
198#elif defined (US3)
199 unsigned : 5; /**< Ignored. */
200 unsigned type: 2; /**< The type of demap operation. */
201#endif
202 unsigned context : 2; /**< Context register selection. */
203 unsigned : 4; /**< Zero. */
204 } __attribute__ ((packed));
205};
206typedef union tlb_demap_addr tlb_demap_addr_t;
207
208/** TLB Synchronous Fault Status Register. */
209union tlb_sfsr_reg {
210 uint64_t value;
211 struct {
212#if defined (US)
213 unsigned long : 40; /**< Implementation dependent. */
214 unsigned asi : 8; /**< ASI. */
215 unsigned : 2;
216 unsigned ft : 7; /**< Fault type. */
217#elif defined (US3)
218 unsigned long : 39; /**< Implementation dependent. */
219 unsigned nf : 1; /**< Non-faulting load. */
220 unsigned asi : 8; /**< ASI. */
221 unsigned tm : 1; /**< I-TLB miss. */
222 unsigned : 3; /**< Reserved. */
223 unsigned ft : 5; /**< Fault type. */
224#endif
225 unsigned e : 1; /**< Side-effect bit. */
226 unsigned ct : 2; /**< Context Register selection. */
227 unsigned pr : 1; /**< Privilege bit. */
228 unsigned w : 1; /**< Write bit. */
229 unsigned ow : 1; /**< Overwrite bit. */
230 unsigned fv : 1; /**< Fault Valid bit. */
231 } __attribute__ ((packed));
232};
233typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
234
235#if defined (US3)
236
237/*
238 * Functions for determining the number of entries in TLBs. They either return
239 * a constant value or a value based on the CPU autodetection.
240 */
241
242/**
243 * Determine the number of entries in the DMMU's small TLB.
244 */
245NO_TRACE static inline uint16_t tlb_dsmall_size(void)
246{
247 return 16;
248}
249
250/**
251 * Determine the number of entries in each DMMU's big TLB.
252 */
253NO_TRACE static inline uint16_t tlb_dbig_size(void)
254{
255 return 512;
256}
257
258/**
259 * Determine the number of entries in the IMMU's small TLB.
260 */
261NO_TRACE static inline uint16_t tlb_ismall_size(void)
262{
263 return 16;
264}
265
266/**
267 * Determine the number of entries in the IMMU's big TLB.
268 */
269NO_TRACE static inline uint16_t tlb_ibig_size(void)
270{
271 if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
272 return 512;
273 else
274 return 128;
275}
276
277#endif
278
279/** Read MMU Primary Context Register.
280 *
281 * @return Current value of Primary Context Register.
282 */
283NO_TRACE static inline uint64_t mmu_primary_context_read(void)
284{
285 return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
286}
287
288/** Write MMU Primary Context Register.
289 *
290 * @param v New value of Primary Context Register.
291 */
292NO_TRACE static inline void mmu_primary_context_write(uint64_t v)
293{
294 asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
295 flush_pipeline();
296}
297
298/** Read MMU Secondary Context Register.
299 *
300 * @return Current value of Secondary Context Register.
301 */
302NO_TRACE static inline uint64_t mmu_secondary_context_read(void)
303{
304 return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
305}
306
307/** Write MMU Primary Context Register.
308 *
309 * @param v New value of Primary Context Register.
310 */
311NO_TRACE static inline void mmu_secondary_context_write(uint64_t v)
312{
313 asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
314 flush_pipeline();
315}
316
317#if defined (US)
318
319/** Read IMMU TLB Data Access Register.
320 *
321 * @param entry TLB Entry index.
322 *
323 * @return Current value of specified IMMU TLB Data Access
324 * Register.
325 */
326NO_TRACE static inline uint64_t itlb_data_access_read(size_t entry)
327{
328 itlb_data_access_addr_t reg;
329
330 reg.value = 0;
331 reg.tlb_entry = entry;
332 return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
333}
334
335/** Write IMMU TLB Data Access Register.
336 *
337 * @param entry TLB Entry index.
338 * @param value Value to be written.
339 */
340NO_TRACE static inline void itlb_data_access_write(size_t entry, uint64_t value)
341{
342 itlb_data_access_addr_t reg;
343
344 reg.value = 0;
345 reg.tlb_entry = entry;
346 asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
347 flush_pipeline();
348}
349
350/** Read DMMU TLB Data Access Register.
351 *
352 * @param entry TLB Entry index.
353 *
354 * @return Current value of specified DMMU TLB Data Access
355 * Register.
356 */
357NO_TRACE static inline uint64_t dtlb_data_access_read(size_t entry)
358{
359 dtlb_data_access_addr_t reg;
360
361 reg.value = 0;
362 reg.tlb_entry = entry;
363 return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
364}
365
366/** Write DMMU TLB Data Access Register.
367 *
368 * @param entry TLB Entry index.
369 * @param value Value to be written.
370 */
371NO_TRACE static inline void dtlb_data_access_write(size_t entry, uint64_t value)
372{
373 dtlb_data_access_addr_t reg;
374
375 reg.value = 0;
376 reg.tlb_entry = entry;
377 asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
378 membar();
379}
380
381/** Read IMMU TLB Tag Read Register.
382 *
383 * @param entry TLB Entry index.
384 *
385 * @return Current value of specified IMMU TLB Tag Read Register.
386 */
387NO_TRACE static inline uint64_t itlb_tag_read_read(size_t entry)
388{
389 itlb_tag_read_addr_t tag;
390
391 tag.value = 0;
392 tag.tlb_entry = entry;
393 return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
394}
395
396/** Read DMMU TLB Tag Read Register.
397 *
398 * @param entry TLB Entry index.
399 *
400 * @return Current value of specified DMMU TLB Tag Read Register.
401 */
402NO_TRACE static inline uint64_t dtlb_tag_read_read(size_t entry)
403{
404 dtlb_tag_read_addr_t tag;
405
406 tag.value = 0;
407 tag.tlb_entry = entry;
408 return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
409}
410
411#elif defined (US3)
412
413
414/** Read IMMU TLB Data Access Register.
415 *
416 * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
417 * @param entry TLB Entry index.
418 *
419 * @return Current value of specified IMMU TLB Data Access
420 * Register.
421 */
422NO_TRACE static inline uint64_t itlb_data_access_read(int tlb, size_t entry)
423{
424 itlb_data_access_addr_t reg;
425
426 reg.value = 0;
427 reg.tlb_number = tlb;
428 reg.local_tlb_entry = entry;
429 return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
430}
431
432/** Write IMMU TLB Data Access Register.
433 * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
434 * @param entry TLB Entry index.
435 * @param value Value to be written.
436 */
437NO_TRACE static inline void itlb_data_access_write(int tlb, size_t entry,
438 uint64_t value)
439{
440 itlb_data_access_addr_t reg;
441
442 reg.value = 0;
443 reg.tlb_number = tlb;
444 reg.local_tlb_entry = entry;
445 asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
446 flush_pipeline();
447}
448
449/** Read DMMU TLB Data Access Register.
450 *
451 * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
452 * @param entry TLB Entry index.
453 *
454 * @return Current value of specified DMMU TLB Data Access
455 * Register.
456 */
457NO_TRACE static inline uint64_t dtlb_data_access_read(int tlb, size_t entry)
458{
459 dtlb_data_access_addr_t reg;
460
461 reg.value = 0;
462 reg.tlb_number = tlb;
463 reg.local_tlb_entry = entry;
464 return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
465}
466
467/** Write DMMU TLB Data Access Register.
468 *
469 * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
470 * @param entry TLB Entry index.
471 * @param value Value to be written.
472 */
473NO_TRACE static inline void dtlb_data_access_write(int tlb, size_t entry,
474 uint64_t value)
475{
476 dtlb_data_access_addr_t reg;
477
478 reg.value = 0;
479 reg.tlb_number = tlb;
480 reg.local_tlb_entry = entry;
481 asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
482 membar();
483}
484
485/** Read IMMU TLB Tag Read Register.
486 *
487 * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
488 * @param entry TLB Entry index.
489 *
490 * @return Current value of specified IMMU TLB Tag Read Register.
491 */
492NO_TRACE static inline uint64_t itlb_tag_read_read(int tlb, size_t entry)
493{
494 itlb_tag_read_addr_t tag;
495
496 tag.value = 0;
497 tag.tlb_number = tlb;
498 tag.local_tlb_entry = entry;
499 return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
500}
501
502/** Read DMMU TLB Tag Read Register.
503 *
504 * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
505 * @param entry TLB Entry index.
506 *
507 * @return Current value of specified DMMU TLB Tag Read Register.
508 */
509NO_TRACE static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry)
510{
511 dtlb_tag_read_addr_t tag;
512
513 tag.value = 0;
514 tag.tlb_number = tlb;
515 tag.local_tlb_entry = entry;
516 return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
517}
518
519#endif
520
521
522/** Write IMMU TLB Tag Access Register.
523 *
524 * @param v Value to be written.
525 */
526NO_TRACE static inline void itlb_tag_access_write(uint64_t v)
527{
528 asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
529 flush_pipeline();
530}
531
532/** Read IMMU TLB Tag Access Register.
533 *
534 * @return Current value of IMMU TLB Tag Access Register.
535 */
536NO_TRACE static inline uint64_t itlb_tag_access_read(void)
537{
538 return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
539}
540
541/** Write DMMU TLB Tag Access Register.
542 *
543 * @param v Value to be written.
544 */
545NO_TRACE static inline void dtlb_tag_access_write(uint64_t v)
546{
547 asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
548 membar();
549}
550
551/** Read DMMU TLB Tag Access Register.
552 *
553 * @return Current value of DMMU TLB Tag Access Register.
554 */
555NO_TRACE static inline uint64_t dtlb_tag_access_read(void)
556{
557 return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
558}
559
560
561/** Write IMMU TLB Data in Register.
562 *
563 * @param v Value to be written.
564 */
565NO_TRACE static inline void itlb_data_in_write(uint64_t v)
566{
567 asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
568 flush_pipeline();
569}
570
571/** Write DMMU TLB Data in Register.
572 *
573 * @param v Value to be written.
574 */
575NO_TRACE static inline void dtlb_data_in_write(uint64_t v)
576{
577 asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
578 membar();
579}
580
581/** Read ITLB Synchronous Fault Status Register.
582 *
583 * @return Current content of I-SFSR register.
584 */
585NO_TRACE static inline uint64_t itlb_sfsr_read(void)
586{
587 return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
588}
589
590/** Write ITLB Synchronous Fault Status Register.
591 *
592 * @param v New value of I-SFSR register.
593 */
594NO_TRACE static inline void itlb_sfsr_write(uint64_t v)
595{
596 asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
597 flush_pipeline();
598}
599
600/** Read DTLB Synchronous Fault Status Register.
601 *
602 * @return Current content of D-SFSR register.
603 */
604NO_TRACE static inline uint64_t dtlb_sfsr_read(void)
605{
606 return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
607}
608
609/** Write DTLB Synchronous Fault Status Register.
610 *
611 * @param v New value of D-SFSR register.
612 */
613NO_TRACE static inline void dtlb_sfsr_write(uint64_t v)
614{
615 asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
616 membar();
617}
618
619/** Read DTLB Synchronous Fault Address Register.
620 *
621 * @return Current content of D-SFAR register.
622 */
623NO_TRACE static inline uint64_t dtlb_sfar_read(void)
624{
625 return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
626}
627
628/** Perform IMMU TLB Demap Operation.
629 *
630 * @param type Selects between context and page demap (and entire MMU
631 * demap on US3).
632 * @param context_encoding Specifies which Context register has Context ID for
633 * demap.
634 * @param page Address which is on the page to be demapped.
635 */
636NO_TRACE static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
637{
638 tlb_demap_addr_t da;
639 page_address_t pg;
640
641 da.value = 0;
642 pg.address = page;
643
644 da.type = type;
645 da.context = context_encoding;
646 da.vpn = pg.vpn;
647
648 /* da.value is the address within the ASI */
649 asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
650
651 flush_pipeline();
652}
653
654/** Perform DMMU TLB Demap Operation.
655 *
656 * @param type Selects between context and page demap (and entire MMU
657 * demap on US3).
658 * @param context_encoding Specifies which Context register has Context ID for
659 * demap.
660 * @param page Address which is on the page to be demapped.
661 */
662NO_TRACE static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
663{
664 tlb_demap_addr_t da;
665 page_address_t pg;
666
667 da.value = 0;
668 pg.address = page;
669
670 da.type = type;
671 da.context = context_encoding;
672 da.vpn = pg.vpn;
673
674 /* da.value is the address within the ASI */
675 asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
676
677 membar();
678}
679
680extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
681extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
682extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);
683
684extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
685
686extern void dump_sfsr_and_sfar(void);
687extern void describe_dmmu_fault(void);
688
689#endif /* !def __ASM__ */
690
691#endif
692
693/** @}
694 */
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