| 1 | /*
|
|---|
| 2 | * Copyright (C) 2005 Jakub Jermar
|
|---|
| 3 | * All rights reserved.
|
|---|
| 4 | *
|
|---|
| 5 | * Redistribution and use in source and binary forms, with or without
|
|---|
| 6 | * modification, are permitted provided that the following conditions
|
|---|
| 7 | * are met:
|
|---|
| 8 | *
|
|---|
| 9 | * - Redistributions of source code must retain the above copyright
|
|---|
| 10 | * notice, this list of conditions and the following disclaimer.
|
|---|
| 11 | * - Redistributions in binary form must reproduce the above copyright
|
|---|
| 12 | * notice, this list of conditions and the following disclaimer in the
|
|---|
| 13 | * documentation and/or other materials provided with the distribution.
|
|---|
| 14 | * - The name of the author may not be used to endorse or promote products
|
|---|
| 15 | * derived from this software without specific prior written permission.
|
|---|
| 16 | *
|
|---|
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
|---|
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
|---|
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|---|
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|---|
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|---|
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|---|
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|---|
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|---|
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
|---|
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|---|
| 27 | */
|
|---|
| 28 |
|
|---|
| 29 | /** @addtogroup sparc64mm
|
|---|
| 30 | * @{
|
|---|
| 31 | */
|
|---|
| 32 | /** @file
|
|---|
| 33 | */
|
|---|
| 34 |
|
|---|
| 35 | #ifndef __sparc64_MMU_H__
|
|---|
| 36 | #define __sparc64_MMU_H__
|
|---|
| 37 |
|
|---|
| 38 | /* LSU Control Register ASI. */
|
|---|
| 39 | #define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */
|
|---|
| 40 |
|
|---|
| 41 | /* I-MMU ASIs. */
|
|---|
| 42 | #define ASI_IMMU 0x50
|
|---|
| 43 | #define ASI_IMMU_TSB_8KB_PTR_REG 0x51
|
|---|
| 44 | #define ASI_IMMU_TSB_64KB_PTR_REG 0x52
|
|---|
| 45 | #define ASI_ITLB_DATA_IN_REG 0x54
|
|---|
| 46 | #define ASI_ITLB_DATA_ACCESS_REG 0x55
|
|---|
| 47 | #define ASI_ITLB_TAG_READ_REG 0x56
|
|---|
| 48 | #define ASI_IMMU_DEMAP 0x57
|
|---|
| 49 |
|
|---|
| 50 | /* Virtual Addresses within ASI_IMMU. */
|
|---|
| 51 | #define VA_IMMU_TAG_TARGET 0x0 /**< IMMU tag target register. */
|
|---|
| 52 | #define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */
|
|---|
| 53 | #define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */
|
|---|
| 54 | #define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */
|
|---|
| 55 |
|
|---|
| 56 | /* D-MMU ASIs. */
|
|---|
| 57 | #define ASI_DMMU 0x58
|
|---|
| 58 | #define ASI_DMMU_TSB_8KB_PTR_REG 0x59
|
|---|
| 59 | #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a
|
|---|
| 60 | #define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b
|
|---|
| 61 | #define ASI_DTLB_DATA_IN_REG 0x5c
|
|---|
| 62 | #define ASI_DTLB_DATA_ACCESS_REG 0x5d
|
|---|
| 63 | #define ASI_DTLB_TAG_READ_REG 0x5e
|
|---|
| 64 | #define ASI_DMMU_DEMAP 0x5f
|
|---|
| 65 |
|
|---|
| 66 | /* Virtual Addresses within ASI_DMMU. */
|
|---|
| 67 | #define VA_DMMU_TAG_TARGET 0x0 /**< DMMU tag target register. */
|
|---|
| 68 | #define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */
|
|---|
| 69 | #define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */
|
|---|
| 70 | #define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */
|
|---|
| 71 | #define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */
|
|---|
| 72 | #define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */
|
|---|
| 73 | #define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */
|
|---|
| 74 | #define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */
|
|---|
| 75 | #define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */
|
|---|
| 76 |
|
|---|
| 77 | #ifndef __ASM__
|
|---|
| 78 |
|
|---|
| 79 | #include <arch/asm.h>
|
|---|
| 80 | #include <arch/barrier.h>
|
|---|
| 81 | #include <arch/types.h>
|
|---|
| 82 | #include <typedefs.h>
|
|---|
| 83 |
|
|---|
| 84 | /** LSU Control Register. */
|
|---|
| 85 | union lsu_cr_reg {
|
|---|
| 86 | uint64_t value;
|
|---|
| 87 | struct {
|
|---|
| 88 | unsigned : 23;
|
|---|
| 89 | unsigned pm : 8;
|
|---|
| 90 | unsigned vm : 8;
|
|---|
| 91 | unsigned pr : 1;
|
|---|
| 92 | unsigned pw : 1;
|
|---|
| 93 | unsigned vr : 1;
|
|---|
| 94 | unsigned vw : 1;
|
|---|
| 95 | unsigned : 1;
|
|---|
| 96 | unsigned fm : 16;
|
|---|
| 97 | unsigned dm : 1; /**< D-MMU enable. */
|
|---|
| 98 | unsigned im : 1; /**< I-MMU enable. */
|
|---|
| 99 | unsigned dc : 1; /**< D-Cache enable. */
|
|---|
| 100 | unsigned ic : 1; /**< I-Cache enable. */
|
|---|
| 101 |
|
|---|
| 102 | } __attribute__ ((packed));
|
|---|
| 103 | };
|
|---|
| 104 | typedef union lsu_cr_reg lsu_cr_reg_t;
|
|---|
| 105 |
|
|---|
| 106 | #endif /* !def __ASM__ */
|
|---|
| 107 |
|
|---|
| 108 | #endif
|
|---|
| 109 |
|
|---|
| 110 | /** @}
|
|---|
| 111 | */
|
|---|
