source: mainline/kernel/arch/sparc64/include/mm/cache_spec.h@ 9d58539

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 9d58539 was 9d58539, checked in by Prutkov Alex <prutkov.alex@…>, 14 years ago

Fixed unix permissions for all files

  • Property mode set to 100644
File size: 2.0 KB
RevLine 
[e25eca80]1/*
2 * Copyright (c) 2008 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[b97b348]29/** @addtogroup sparc64mm
[e25eca80]30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_sparc64_CACHE_SPEC_H_
36#define KERN_sparc64_CACHE_SPEC_H_
37
38/*
39 * The following macros are valid for the following processors:
40 *
[b97b348]41 * UltraSPARC, UltraSPARC II, UltraSPARC IIi, UltraSPARC III,
42 * UltraSPARC III+, UltraSPARC IV, UltraSPARC IV+
43 *
[e25eca80]44 * Should we support other UltraSPARC processors, we need to make sure that
45 * the macros are defined correctly for them.
46 */
[b97b348]47
[965dc18]48#if defined (US)
[b97b348]49 #define DCACHE_SIZE (16 * 1024)
[965dc18]50#elif defined (US3)
[b97b348]51 #define DCACHE_SIZE (64 * 1024)
[965dc18]52#endif
[b97b348]53
54#define DCACHE_LINE_SIZE 32
55#define DCACHE_TAG_SHIFT 2
[e25eca80]56
57#endif
58
59/** @}
60 */
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