source: mainline/kernel/arch/sparc64/include/cpu.h@ 8ccd2ea

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 8ccd2ea was 2057572, checked in by Jakub Jermar <jakub@…>, 18 years ago

The Ultimate Solution To Illegal Virtual Aliases.
It is better to avoid them completely than to fight them.
Switch the sparc64 port to 16K pages. The TLBs and TSBs
continue to operate with 8K pages only. Page tables and
other generic parts operate with 16K pages.

Because the MMU doesn't support 16K directly, each 16K
page is emulated by a pair of 8K pages. With 16K pages,
illegal aliases cannot be created in 16K D-cache.

  • Property mode set to 100644
File size: 2.3 KB
Line 
1/*
2 * Copyright (c) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup sparc64
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_sparc64_CPU_H_
36#define KERN_sparc64_CPU_H_
37
38#include <arch/types.h>
39#include <arch/register.h>
40#include <arch/asm.h>
41
42#ifdef CONFIG_SMP
43#include <arch/mm/cache.h>
44#endif
45
46#define MANUF_FUJITSU 0x04
47#define MANUF_ULTRASPARC 0x17 /**< UltraSPARC I, UltraSPARC II */
48#define MANUF_SUN 0x3e
49
50#define IMPL_ULTRASPARCI 0x10
51#define IMPL_ULTRASPARCII 0x11
52#define IMPL_ULTRASPARCII_I 0x12
53#define IMPL_ULTRASPARCII_E 0x13
54#define IMPL_ULTRASPARCIII 0x15
55#define IMPL_ULTRASPARCIV_PLUS 0x19
56
57#define IMPL_SPARC64V 0x5
58
59typedef struct {
60 uint32_t mid; /**< Processor ID as read from
61 UPA_CONFIG. */
62 ver_reg_t ver;
63 uint32_t clock_frequency; /**< Processor frequency in Hz. */
64 uint64_t next_tick_cmpr; /**< Next clock interrupt should be
65 generated when the TICK register
66 matches this value. */
67} cpu_arch_t;
68
69#endif
70
71/** @}
72 */
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