source: mainline/kernel/arch/sparc64/include/barrier.h@ 4a4c8bcf

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 4a4c8bcf was 7a0359b, checked in by Martin Decky <martin@…>, 15 years ago

improve kernel function tracing

  • add support for more generic kernel sources
  • replace attribute((no_instrument_function)) with NO_TRACE macro (shorter and for future compatibility with different compilers)
  • to be on the safe side, do not instrument most of the inline and static functions (plus some specific non-static functions)

collateral code cleanup (no change in functionality)

  • Property mode set to 100644
File size: 3.5 KB
RevLine 
[2a99fa8]1/*
[df4ed85]2 * Copyright (c) 2005 Jakub Jermar
[2a99fa8]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[7a0359b]29/** @addtogroup sparc64
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[ed166f7]35#ifndef KERN_sparc64_BARRIER_H_
36#define KERN_sparc64_BARRIER_H_
[2a99fa8]37
[7a0359b]38#include <trace.h>
39
[c8e99bb]40#ifdef KERNEL
[7a0359b]41
[c8e99bb]42#include <typedefs.h>
[7a0359b]43
[c8e99bb]44#else
[7a0359b]45
[c8e99bb]46#include <stdint.h>
[7a0359b]47
[c8e99bb]48#endif
49
[2a99fa8]50/*
[1ecdbb0]51 * Our critical section barriers are prepared for the weakest RMO memory model.
[2a99fa8]52 */
[7a0359b]53#define CS_ENTER_BARRIER() \
54 asm volatile ( \
55 "membar #LoadLoad | #LoadStore\n" \
56 ::: "memory" \
[1ecdbb0]57 )
[7a0359b]58
59#define CS_LEAVE_BARRIER() \
60 asm volatile ( \
61 "membar #StoreStore\n" \
62 "membar #LoadStore\n" \
63 ::: "memory" \
64 )
65
66#define memory_barrier() \
67 asm volatile ( \
68 "membar #LoadLoad | #StoreStore\n" \
69 ::: "memory" \
70 )
71
72#define read_barrier() \
73 asm volatile ( \
74 "membar #LoadLoad\n" \
75 ::: "memory" \
[1ecdbb0]76 )
[2a99fa8]77
[7a0359b]78#define write_barrier() \
79 asm volatile ( \
80 "membar #StoreStore\n" \
81 ::: "memory" \
82 )
[2a99fa8]83
[7a0359b]84#define flush(a) \
85 asm volatile ( \
86 "flush %[reg]\n" \
87 :: [reg] "r" ((a)) \
88 : "memory" \
89 )
[e25eca80]90
[c711efe]91/** Flush Instruction pipeline. */
[7a0359b]92NO_TRACE static inline void flush_pipeline(void)
[c52ed6b]93{
[c8e99bb]94 uint64_t pc;
[7a0359b]95
[c52ed6b]96 /*
[9ea8a7ca]97 * The FLUSH instruction takes address parameter.
98 * As such, it may trap if the address is not found in DTLB.
[32fffef0]99 *
100 * The entire kernel text is mapped by a locked ITLB and
101 * DTLB entries. Therefore, when this function is called,
[c8e99bb]102 * the %pc register will always be in the range mapped by
[32fffef0]103 * DTLB.
[7a0359b]104 *
[c52ed6b]105 */
[7a0359b]106
107 asm volatile (
108 "rd %%pc, %[pc]\n"
109 "flush %[pc]\n"
110 : [pc] "=&r" (pc)
[c8e99bb]111 );
[c52ed6b]112}
[b00fdde]113
[9ea8a7ca]114/** Memory Barrier instruction. */
[7a0359b]115NO_TRACE static inline void membar(void)
[b5e0bb8]116{
[7a0359b]117 asm volatile (
118 "membar #Sync\n"
119 );
[b5e0bb8]120}
121
[723060a]122#if defined (US)
123
[7a0359b]124#define FLUSH_INVAL_MIN 4
[e25eca80]125
[7a0359b]126#define smc_coherence(a) \
127 do { \
128 write_barrier(); \
129 flush((a)); \
130 } while (0)
131
132#define smc_coherence_block(a, l) \
133 do { \
134 unsigned long i; \
135 write_barrier(); \
136 \
137 for (i = 0; i < (l); i += FLUSH_INVAL_MIN) \
138 flush((void *)(a) + i); \
139 } while (0)
[d5087aa]140
[723060a]141#elif defined (US3)
142
[7a0359b]143#define smc_coherence(a) \
144 do { \
145 write_barrier(); \
146 flush_pipeline(); \
147 } while (0)
[723060a]148
[7a0359b]149#define smc_coherence_block(a, l) \
150 do { \
151 write_barrier(); \
152 flush_pipeline(); \
153 } while (0)
[723060a]154
[7a0359b]155#endif /* defined(US3) */
[723060a]156
[2a99fa8]157#endif
[b45c443]158
[0ffa3ef5]159/** @}
[b45c443]160 */
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