[2a99fa8] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2005 Jakub Jermar
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[2a99fa8] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[7a0359b] | 29 | /** @addtogroup sparc64
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[ed166f7] | 35 | #ifndef KERN_sparc64_BARRIER_H_
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| 36 | #define KERN_sparc64_BARRIER_H_
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[2a99fa8] | 37 |
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[7a0359b] | 38 | #include <trace.h>
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| 39 |
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[c8e99bb] | 40 | #ifdef KERNEL
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[7a0359b] | 41 |
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[c8e99bb] | 42 | #include <typedefs.h>
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[7a0359b] | 43 |
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[c8e99bb] | 44 | #else
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[7a0359b] | 45 |
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[c8e99bb] | 46 | #include <stdint.h>
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[7a0359b] | 47 |
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[c8e99bb] | 48 | #endif
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| 49 |
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[2a99fa8] | 50 | /*
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[1ecdbb0] | 51 | * Our critical section barriers are prepared for the weakest RMO memory model.
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[2a99fa8] | 52 | */
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[7a0359b] | 53 | #define CS_ENTER_BARRIER() \
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| 54 | asm volatile ( \
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| 55 | "membar #LoadLoad | #LoadStore\n" \
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| 56 | ::: "memory" \
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[1ecdbb0] | 57 | )
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[7a0359b] | 58 |
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| 59 | #define CS_LEAVE_BARRIER() \
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| 60 | asm volatile ( \
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| 61 | "membar #StoreStore\n" \
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| 62 | "membar #LoadStore\n" \
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| 63 | ::: "memory" \
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| 64 | )
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| 65 |
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| 66 | #define memory_barrier() \
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| 67 | asm volatile ( \
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| 68 | "membar #LoadLoad | #StoreStore\n" \
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| 69 | ::: "memory" \
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| 70 | )
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| 71 |
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| 72 | #define read_barrier() \
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| 73 | asm volatile ( \
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| 74 | "membar #LoadLoad\n" \
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| 75 | ::: "memory" \
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[1ecdbb0] | 76 | )
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[2a99fa8] | 77 |
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[7a0359b] | 78 | #define write_barrier() \
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| 79 | asm volatile ( \
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| 80 | "membar #StoreStore\n" \
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| 81 | ::: "memory" \
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| 82 | )
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[2a99fa8] | 83 |
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[7a0359b] | 84 | #define flush(a) \
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| 85 | asm volatile ( \
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| 86 | "flush %[reg]\n" \
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| 87 | :: [reg] "r" ((a)) \
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| 88 | : "memory" \
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| 89 | )
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[e25eca80] | 90 |
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[c711efe] | 91 | /** Flush Instruction pipeline. */
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[7a0359b] | 92 | NO_TRACE static inline void flush_pipeline(void)
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[c52ed6b] | 93 | {
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[c8e99bb] | 94 | uint64_t pc;
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[7a0359b] | 95 |
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[c52ed6b] | 96 | /*
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[9ea8a7ca] | 97 | * The FLUSH instruction takes address parameter.
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| 98 | * As such, it may trap if the address is not found in DTLB.
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[32fffef0] | 99 | *
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| 100 | * The entire kernel text is mapped by a locked ITLB and
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| 101 | * DTLB entries. Therefore, when this function is called,
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[c8e99bb] | 102 | * the %pc register will always be in the range mapped by
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[32fffef0] | 103 | * DTLB.
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[7a0359b] | 104 | *
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[c52ed6b] | 105 | */
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[7a0359b] | 106 |
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| 107 | asm volatile (
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| 108 | "rd %%pc, %[pc]\n"
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| 109 | "flush %[pc]\n"
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| 110 | : [pc] "=&r" (pc)
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[c8e99bb] | 111 | );
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[c52ed6b] | 112 | }
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[b00fdde] | 113 |
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[9ea8a7ca] | 114 | /** Memory Barrier instruction. */
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[7a0359b] | 115 | NO_TRACE static inline void membar(void)
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[b5e0bb8] | 116 | {
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[7a0359b] | 117 | asm volatile (
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| 118 | "membar #Sync\n"
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| 119 | );
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[b5e0bb8] | 120 | }
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| 121 |
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[723060a] | 122 | #if defined (US)
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| 123 |
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[7a0359b] | 124 | #define FLUSH_INVAL_MIN 4
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[e25eca80] | 125 |
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[7a0359b] | 126 | #define smc_coherence(a) \
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| 127 | do { \
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| 128 | write_barrier(); \
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| 129 | flush((a)); \
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| 130 | } while (0)
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| 131 |
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| 132 | #define smc_coherence_block(a, l) \
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| 133 | do { \
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| 134 | unsigned long i; \
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| 135 | write_barrier(); \
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| 136 | \
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| 137 | for (i = 0; i < (l); i += FLUSH_INVAL_MIN) \
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| 138 | flush((void *)(a) + i); \
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| 139 | } while (0)
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[d5087aa] | 140 |
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[723060a] | 141 | #elif defined (US3)
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| 142 |
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[7a0359b] | 143 | #define smc_coherence(a) \
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| 144 | do { \
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| 145 | write_barrier(); \
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| 146 | flush_pipeline(); \
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| 147 | } while (0)
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[723060a] | 148 |
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[7a0359b] | 149 | #define smc_coherence_block(a, l) \
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| 150 | do { \
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| 151 | write_barrier(); \
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| 152 | flush_pipeline(); \
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| 153 | } while (0)
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[723060a] | 154 |
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[7a0359b] | 155 | #endif /* defined(US3) */
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[723060a] | 156 |
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[2a99fa8] | 157 | #endif
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[b45c443] | 158 |
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[0ffa3ef5] | 159 | /** @}
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[b45c443] | 160 | */
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