source: mainline/kernel/arch/sparc64/include/atomic.h@ 5954241

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 5954241 was 40239b9, checked in by Jakub Jermar <jakub@…>, 15 years ago

Fix a couple of occurrences of obsolete branch instruction with proper SPARC V9
branches. More dispensable NOP instructions killed.

  • Property mode set to 100644
File size: 3.5 KB
RevLine 
[2a99fa8]1/*
[df4ed85]2 * Copyright (c) 2005 Jakub Jermar
[2a99fa8]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[228666c]29/** @addtogroup sparc64
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[ed166f7]35#ifndef KERN_sparc64_ATOMIC_H_
36#define KERN_sparc64_ATOMIC_H_
[2a99fa8]37
[86b31ba9]38#include <arch/barrier.h>
[d99c1d2]39#include <typedefs.h>
[bf29fe5]40#include <preemption.h>
[59e07c91]41
[0fad93a]42/** Atomic add operation.
43 *
44 * Use atomic compare and swap operation to atomically add signed value.
45 *
46 * @param val Atomic variable.
[228666c]47 * @param i Signed value to be added.
[0fad93a]48 *
49 * @return Value of the atomic variable as it existed before addition.
[228666c]50 *
[2a99fa8]51 */
[228666c]52static inline atomic_count_t atomic_add(atomic_t *val, atomic_count_t i)
[0fad93a]53{
[228666c]54 atomic_count_t a;
55 atomic_count_t b;
56
[06e1e95]57 do {
[228666c]58 volatile uintptr_t ptr = (uintptr_t) &val->count;
59
60 a = *((atomic_count_t *) ptr);
[06e1e95]61 b = a + i;
[228666c]62
63 asm volatile (
64 "casx %0, %2, %1\n"
65 : "+m" (*((atomic_count_t *) ptr)),
66 "+r" (b)
67 : "r" (a)
68 );
[06e1e95]69 } while (a != b);
[228666c]70
[0fad93a]71 return a;
72}
[2a99fa8]73
[228666c]74static inline atomic_count_t atomic_preinc(atomic_t *val)
[9a2d6e1]75{
76 return atomic_add(val, 1) + 1;
77}
78
[228666c]79static inline atomic_count_t atomic_postinc(atomic_t *val)
[9a2d6e1]80{
81 return atomic_add(val, 1);
82}
83
[228666c]84static inline atomic_count_t atomic_predec(atomic_t *val)
[9a2d6e1]85{
86 return atomic_add(val, -1) - 1;
87}
88
[228666c]89static inline atomic_count_t atomic_postdec(atomic_t *val)
[9a2d6e1]90{
[8eb36b0]91 return atomic_add(val, -1);
[9a2d6e1]92}
93
[10c071e]94static inline void atomic_inc(atomic_t *val)
95{
[0fad93a]96 (void) atomic_add(val, 1);
[2a99fa8]97}
98
[10c071e]99static inline void atomic_dec(atomic_t *val)
100{
[0fad93a]101 (void) atomic_add(val, -1);
[2a99fa8]102}
103
[228666c]104static inline atomic_count_t test_and_set(atomic_t *val)
[86b31ba9]105{
[228666c]106 atomic_count_t v = 1;
107 volatile uintptr_t ptr = (uintptr_t) &val->count;
108
109 asm volatile (
110 "casx %0, %2, %1\n"
111 : "+m" (*((atomic_count_t *) ptr)),
112 "+r" (v)
113 : "r" (0)
114 );
115
[86b31ba9]116 return v;
117}
118
119static inline void atomic_lock_arch(atomic_t *val)
120{
[228666c]121 atomic_count_t tmp1 = 1;
122 atomic_count_t tmp2 = 0;
123
124 volatile uintptr_t ptr = (uintptr_t) &val->count;
125
[bf29fe5]126 preemption_disable();
[228666c]127
[e7b7be3f]128 asm volatile (
[228666c]129 "0:\n"
130 "casx %0, %3, %1\n"
131 "brz %1, 2f\n"
132 "nop\n"
133 "1:\n"
134 "ldx %0, %2\n"
135 "brz %2, 0b\n"
136 "nop\n"
[40239b9]137 "ba,a %%xcc, 1b\n"
[228666c]138 "2:\n"
139 : "+m" (*((atomic_count_t *) ptr)),
140 "+r" (tmp1),
141 "+r" (tmp2)
142 : "r" (0)
[86b31ba9]143 );
144
145 /*
146 * Prevent critical section code from bleeding out this way up.
147 */
148 CS_ENTER_BARRIER();
149}
150
[2a99fa8]151#endif
[b45c443]152
[0ffa3ef5]153/** @}
[b45c443]154 */
Note: See TracBrowser for help on using the repository browser.