[2a99fa8] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2005 Jakub Jermar
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[2a99fa8] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[228666c] | 29 | /** @addtogroup sparc64
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[ed166f7] | 35 | #ifndef KERN_sparc64_ATOMIC_H_
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| 36 | #define KERN_sparc64_ATOMIC_H_
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[2a99fa8] | 37 |
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[86b31ba9] | 38 | #include <arch/barrier.h>
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[d99c1d2] | 39 | #include <typedefs.h>
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[bf29fe5] | 40 | #include <preemption.h>
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[7a0359b] | 41 | #include <trace.h>
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[59e07c91] | 42 |
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[0fad93a] | 43 | /** Atomic add operation.
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| 44 | *
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| 45 | * Use atomic compare and swap operation to atomically add signed value.
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| 46 | *
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| 47 | * @param val Atomic variable.
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[228666c] | 48 | * @param i Signed value to be added.
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[0fad93a] | 49 | *
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| 50 | * @return Value of the atomic variable as it existed before addition.
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[228666c] | 51 | *
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[2a99fa8] | 52 | */
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[7a0359b] | 53 | NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val,
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| 54 | atomic_count_t i)
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[0fad93a] | 55 | {
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[228666c] | 56 | atomic_count_t a;
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| 57 | atomic_count_t b;
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| 58 |
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[06e1e95] | 59 | do {
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[228666c] | 60 | volatile uintptr_t ptr = (uintptr_t) &val->count;
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| 61 |
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| 62 | a = *((atomic_count_t *) ptr);
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[06e1e95] | 63 | b = a + i;
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[228666c] | 64 |
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| 65 | asm volatile (
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| 66 | "casx %0, %2, %1\n"
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| 67 | : "+m" (*((atomic_count_t *) ptr)),
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| 68 | "+r" (b)
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| 69 | : "r" (a)
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| 70 | );
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[06e1e95] | 71 | } while (a != b);
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[228666c] | 72 |
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[0fad93a] | 73 | return a;
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| 74 | }
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[2a99fa8] | 75 |
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[7a0359b] | 76 | NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val)
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[9a2d6e1] | 77 | {
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| 78 | return atomic_add(val, 1) + 1;
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| 79 | }
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| 80 |
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[7a0359b] | 81 | NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val)
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[9a2d6e1] | 82 | {
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| 83 | return atomic_add(val, 1);
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| 84 | }
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| 85 |
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[7a0359b] | 86 | NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val)
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[9a2d6e1] | 87 | {
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| 88 | return atomic_add(val, -1) - 1;
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| 89 | }
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| 90 |
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[7a0359b] | 91 | NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val)
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[9a2d6e1] | 92 | {
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[8eb36b0] | 93 | return atomic_add(val, -1);
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[9a2d6e1] | 94 | }
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| 95 |
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[7a0359b] | 96 | NO_TRACE static inline void atomic_inc(atomic_t *val)
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[10c071e] | 97 | {
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[0fad93a] | 98 | (void) atomic_add(val, 1);
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[2a99fa8] | 99 | }
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| 100 |
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[7a0359b] | 101 | NO_TRACE static inline void atomic_dec(atomic_t *val)
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[10c071e] | 102 | {
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[0fad93a] | 103 | (void) atomic_add(val, -1);
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[2a99fa8] | 104 | }
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| 105 |
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[7a0359b] | 106 | NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val)
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[86b31ba9] | 107 | {
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[228666c] | 108 | atomic_count_t v = 1;
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| 109 | volatile uintptr_t ptr = (uintptr_t) &val->count;
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| 110 |
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| 111 | asm volatile (
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| 112 | "casx %0, %2, %1\n"
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| 113 | : "+m" (*((atomic_count_t *) ptr)),
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| 114 | "+r" (v)
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| 115 | : "r" (0)
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| 116 | );
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| 117 |
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[86b31ba9] | 118 | return v;
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| 119 | }
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| 120 |
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[7a0359b] | 121 | NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
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[86b31ba9] | 122 | {
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[228666c] | 123 | atomic_count_t tmp1 = 1;
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| 124 | atomic_count_t tmp2 = 0;
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| 125 |
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| 126 | volatile uintptr_t ptr = (uintptr_t) &val->count;
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| 127 |
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[bf29fe5] | 128 | preemption_disable();
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[228666c] | 129 |
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[e7b7be3f] | 130 | asm volatile (
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[228666c] | 131 | "0:\n"
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| 132 | "casx %0, %3, %1\n"
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| 133 | "brz %1, 2f\n"
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| 134 | "nop\n"
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| 135 | "1:\n"
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| 136 | "ldx %0, %2\n"
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| 137 | "brz %2, 0b\n"
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| 138 | "nop\n"
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[40239b9] | 139 | "ba,a %%xcc, 1b\n"
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[228666c] | 140 | "2:\n"
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| 141 | : "+m" (*((atomic_count_t *) ptr)),
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| 142 | "+r" (tmp1),
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| 143 | "+r" (tmp2)
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| 144 | : "r" (0)
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[86b31ba9] | 145 | );
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| 146 |
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| 147 | /*
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| 148 | * Prevent critical section code from bleeding out this way up.
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| 149 | */
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| 150 | CS_ENTER_BARRIER();
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| 151 | }
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| 152 |
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[2a99fa8] | 153 | #endif
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[b45c443] | 154 |
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[0ffa3ef5] | 155 | /** @}
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[b45c443] | 156 | */
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