source: mainline/kernel/arch/riscv64/src/riscv64.c@ d776329b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d776329b was 8b6aa39, checked in by Martin Decky <martin@…>, 9 years ago

dummy/fake support for RISC-V (RV64G)
it compiles and the boot loader extracts the system components, but otherwise the source serves only as a placeholder for future working implementation

  • Property mode set to 100644
File size: 2.9 KB
Line 
1/*
2 * Copyright (c) 2016 Martin Decky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup riscv64
30 * @{
31 */
32/** @file
33 */
34
35#include <arch.h>
36#include <typedefs.h>
37#include <arch/interrupt.h>
38#include <arch/asm.h>
39
40#include <func.h>
41#include <config.h>
42#include <errno.h>
43#include <context.h>
44#include <fpu_context.h>
45#include <interrupt.h>
46#include <syscall/copy.h>
47#include <ddi/irq.h>
48#include <proc/thread.h>
49#include <console/console.h>
50#include <memstr.h>
51
52char memcpy_from_uspace_failover_address;
53char memcpy_to_uspace_failover_address;
54
55arch_ops_t riscv64_ops = {
56};
57
58arch_ops_t *arch_ops = &riscv64_ops;
59
60void calibrate_delay_loop(void)
61{
62}
63
64/** Construct function pointer
65 *
66 * @param fptr function pointer structure
67 * @param addr function address
68 * @param caller calling function address
69 *
70 * @return address of the function pointer
71 *
72 */
73void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
74{
75 return addr;
76}
77
78void arch_reboot(void)
79{
80}
81
82void irq_initialize_arch(irq_t *irq)
83{
84 (void) irq;
85}
86
87void istate_decode(istate_t *istate)
88{
89 (void) istate;
90}
91
92int context_save_arch(context_t *ctx)
93{
94 return 1;
95}
96
97void context_restore_arch(context_t *ctx)
98{
99 while (true);
100}
101
102void fpu_init(void)
103{
104}
105
106void fpu_context_save(fpu_context_t *ctx)
107{
108}
109
110void fpu_context_restore(fpu_context_t *ctx)
111{
112}
113
114int memcpy_from_uspace(void *dst, const void *uspace_src, size_t size)
115{
116 return EOK;
117}
118
119int memcpy_to_uspace(void *uspace_dst, const void *src, size_t size)
120{
121 return EOK;
122}
123
124void early_putchar(wchar_t ch)
125{
126}
127
128/** @}
129 */
Note: See TracBrowser for help on using the repository browser.