source: mainline/kernel/arch/riscv64/src/mm/page.c@ 6c742f5e

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 6c742f5e was ccc362a1, checked in by Martin Decky <martin@…>, 8 years ago

riscv64: memory management routines, reflecting the latest Privileged Architecture specification (1.10)

  • Property mode set to 100644
File size: 3.0 KB
RevLine 
[8b6aa39]1/*
2 * Copyright (c) 2016 Martin Decky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup riscv64mm
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/mm/page.h>
36#include <genarch/mm/page_pt.h>
37#include <arch/mm/frame.h>
38#include <mm/frame.h>
39#include <mm/page.h>
40#include <mm/as.h>
41#include <align.h>
42#include <config.h>
43#include <func.h>
44#include <arch/interrupt.h>
45#include <arch/asm.h>
46#include <debug.h>
47#include <print.h>
48#include <interrupt.h>
49
[ccc362a1]50#define SATP_PFN_MASK UINT64_C(0x00000fffffffffff)
51
52#define SATP_MODE_MASK UINT64_C(0xf000000000000000)
53#define SATP_MODE_BARE UINT64_C(0x0000000000000000)
54#define SATP_MODE_SV39 UINT64_C(0x8000000000000000)
55#define SATP_MODE_SV48 UINT64_C(0x9000000000000000)
56
[8b6aa39]57void page_arch_init(void)
58{
[ccc362a1]59 if (config.cpu_active == 1) {
[8b6aa39]60 page_mapping_operations = &pt_mapping_operations;
[ccc362a1]61
62 page_table_lock(AS_KERNEL, true);
63
64 /*
65 * PA2KA(identity) mapping for all low-memory frames.
66 */
67 for (uintptr_t cur = 0;
68 cur < min(config.identity_size, config.physmem_end);
69 cur += FRAME_SIZE)
70 page_mapping_insert(AS_KERNEL, PA2KA(cur), cur,
71 PAGE_GLOBAL | PAGE_CACHEABLE | PAGE_EXEC | PAGE_WRITE | PAGE_READ);
72
73 page_table_unlock(AS_KERNEL, true);
74
75 // FIXME: register page fault extension handler
76
77 write_satp((uintptr_t) AS_KERNEL->genarch.page_table);
78
79 /* The boot page table is no longer needed. */
80 // FIXME: frame_mark_available(pt_frame, 1);
81 }
[8b6aa39]82}
83
84void page_fault(unsigned int n __attribute__((unused)), istate_t *istate)
85{
86}
87
[ccc362a1]88void write_satp(uintptr_t ptl0)
89{
90 uint64_t satp = ((ptl0 >> FRAME_WIDTH) & SATP_PFN_MASK) |
91 SATP_MODE_SV48;
92
93 asm volatile (
94 "csrw sptbr, %[satp]\n"
95 :: [satp] "r" (satp)
96 );
97}
98
[8b6aa39]99/** @}
100 */
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