source: mainline/kernel/arch/ppc64/src/asm.S@ ac0e791

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ac0e791 was df4ed85, checked in by Jakub Jermar <jakub@…>, 19 years ago

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1#
2# Copyright (c) 2006 Martin Decky
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29#include <arch/asm/regname.h>
30
31.text
32
33.global userspace_asm
34.global iret
35.global iret_syscall
36.global memsetb
37.global memcpy
38.global memcpy_from_uspace
39.global memcpy_to_uspace
40.global memcpy_from_uspace_failover_address
41.global memcpy_to_uspace_failover_address
42
43userspace_asm:
44
45 # r3 = uspace_uarg
46 # r4 = stack
47 # r5 = entry
48
49 # disable interrupts
50
51 mfmsr r31
52 rlwinm r31, r31, 0, 17, 15
53 mtmsr r31
54
55 # set entry point
56
57 mtsrr0 r5
58
59 # set problem state, enable interrupts
60
61 ori r31, r31, msr_pr
62 ori r31, r31, msr_ee
63 mtsrr1 r31
64
65 # set stack
66
67 mr sp, r4
68
69 # jump to userspace
70
71 rfi
72
73iret:
74
75 # disable interrupts
76
77 mfmsr r31
78 rlwinm r31, r31, 0, 17, 15
79 mtmsr r31
80
81 lwz r0, 8(sp)
82 lwz r2, 12(sp)
83 lwz r3, 16(sp)
84 lwz r4, 20(sp)
85 lwz r5, 24(sp)
86 lwz r6, 28(sp)
87 lwz r7, 32(sp)
88 lwz r8, 36(sp)
89 lwz r9, 40(sp)
90 lwz r10, 44(sp)
91 lwz r11, 48(sp)
92 lwz r13, 52(sp)
93 lwz r14, 56(sp)
94 lwz r15, 60(sp)
95 lwz r16, 64(sp)
96 lwz r17, 68(sp)
97 lwz r18, 72(sp)
98 lwz r19, 76(sp)
99 lwz r20, 80(sp)
100 lwz r21, 84(sp)
101 lwz r22, 88(sp)
102 lwz r23, 92(sp)
103 lwz r24, 96(sp)
104 lwz r25, 100(sp)
105 lwz r26, 104(sp)
106 lwz r27, 108(sp)
107 lwz r28, 112(sp)
108 lwz r29, 116(sp)
109 lwz r30, 120(sp)
110 lwz r31, 124(sp)
111
112 lwz r12, 128(sp)
113 mtcr r12
114
115 lwz r12, 132(sp)
116 mtsrr0 r12
117
118 lwz r12, 136(sp)
119 mtsrr1 r12
120
121 lwz r12, 140(sp)
122 mtlr r12
123
124 lwz r12, 144(sp)
125 mtctr r12
126
127 lwz r12, 148(sp)
128 mtxer r12
129
130 lwz r12, 152(sp)
131 lwz sp, 156(sp)
132
133 rfi
134
135iret_syscall:
136
137 # reset decrementer
138
139 li r31, 1000
140 mtdec r31
141
142 # disable interrupts
143
144 mfmsr r31
145 rlwinm r31, r31, 0, 17, 15
146 mtmsr r31
147
148 lwz r0, 8(sp)
149 lwz r2, 12(sp)
150 lwz r4, 20(sp)
151 lwz r5, 24(sp)
152 lwz r6, 28(sp)
153 lwz r7, 32(sp)
154 lwz r8, 36(sp)
155 lwz r9, 40(sp)
156 lwz r10, 44(sp)
157 lwz r11, 48(sp)
158 lwz r13, 52(sp)
159 lwz r14, 56(sp)
160 lwz r15, 60(sp)
161 lwz r16, 64(sp)
162 lwz r17, 68(sp)
163 lwz r18, 72(sp)
164 lwz r19, 76(sp)
165 lwz r20, 80(sp)
166 lwz r21, 84(sp)
167 lwz r22, 88(sp)
168 lwz r23, 92(sp)
169 lwz r24, 96(sp)
170 lwz r25, 100(sp)
171 lwz r26, 104(sp)
172 lwz r27, 108(sp)
173 lwz r28, 112(sp)
174 lwz r29, 116(sp)
175 lwz r30, 120(sp)
176 lwz r31, 124(sp)
177
178 lwz r12, 128(sp)
179 mtcr r12
180
181 lwz r12, 132(sp)
182 mtsrr0 r12
183
184 lwz r12, 136(sp)
185 mtsrr1 r12
186
187 lwz r12, 140(sp)
188 mtlr r12
189
190 lwz r12, 144(sp)
191 mtctr r12
192
193 lwz r12, 148(sp)
194 mtxer r12
195
196 lwz r12, 152(sp)
197 lwz sp, 156(sp)
198
199 rfi
200
201memsetb:
202 rlwimi r5, r5, 8, 16, 23
203 rlwimi r5, r5, 16, 0, 15
204
205 addi r14, r3, -4
206
207 cmplwi 0, r4, 4
208 blt 7f
209
210 stwu r5, 4(r14)
211 beqlr
212
213 andi. r15, r14, 3
214 add r4, r15, r4
215 subf r14, r15, r14
216 srwi r15, r4, 2
217 mtctr r15
218
219 bdz 6f
220
221 1:
222 stwu r5, 4(r14)
223 bdnz 1b
224
225 6:
226
227 andi. r4, r4, 3
228
229 7:
230
231 cmpwi 0, r4, 0
232 beqlr
233
234 mtctr r4
235 addi r6, r6, 3
236
237 8:
238
239 stbu r5, 1(r14)
240 bdnz 8b
241
242 blr
243
244memcpy:
245memcpy_from_uspace:
246memcpy_to_uspace:
247
248 srwi. r7, r5, 3
249 addi r6, r3, -4
250 addi r4, r4, -4
251 beq 2f
252
253 andi. r0, r6, 3
254 mtctr r7
255 bne 5f
256
257 1:
258
259 lwz r7, 4(r4)
260 lwzu r8, 8(r4)
261 stw r7, 4(r6)
262 stwu r8, 8(r6)
263 bdnz 1b
264
265 andi. r5, r5, 7
266
267 2:
268
269 cmplwi 0, r5, 4
270 blt 3f
271
272 lwzu r0, 4(r4)
273 addi r5, r5, -4
274 stwu r0, 4(r6)
275
276 3:
277
278 cmpwi 0, r5, 0
279 beqlr
280 mtctr r5
281 addi r4, r4, 3
282 addi r6, r6, 3
283
284 4:
285
286 lbzu r0, 1(r4)
287 stbu r0, 1(r6)
288 bdnz 4b
289 blr
290
291 5:
292
293 subfic r0, r0, 4
294 mtctr r0
295
296 6:
297
298 lbz r7, 4(r4)
299 addi r4, r4, 1
300 stb r7, 4(r6)
301 addi r6, r6, 1
302 bdnz 6b
303 subf r5, r0, r5
304 rlwinm. r7, r5, 32-3, 3, 31
305 beq 2b
306 mtctr r7
307 b 1b
308
309memcpy_from_uspace_failover_address:
310memcpy_to_uspace_failover_address:
311 b memcpy_from_uspace_failover_address
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