[602c9101] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2005 Martin Decky
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[602c9101] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[06e1e95] | 29 | /** @addtogroup ppc64mm
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[06e1e95] | 35 | #ifndef KERN_ppc64_PAGE_H_
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| 36 | #define KERN_ppc64_PAGE_H_
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[602c9101] | 37 |
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| 38 | #include <arch/mm/frame.h>
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| 39 |
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| 40 | #define PAGE_WIDTH FRAME_WIDTH
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| 41 | #define PAGE_SIZE FRAME_SIZE
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| 42 |
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| 43 | #ifdef KERNEL
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| 44 |
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| 45 | #ifndef __ASM__
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[7f1c620] | 46 | # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
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| 47 | # define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
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[602c9101] | 48 | #else
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| 49 | # define KA2PA(x) ((x) - 0x80000000)
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| 50 | # define PA2KA(x) ((x) + 0x80000000)
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| 51 | #endif
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| 52 |
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[48c1ef9] | 53 | /*
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| 54 | * Implementation of generic 4-level page table interface,
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| 55 | * the hardware Page Hash Table is used as cache.
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| 56 | *
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| 57 | * Page table layout:
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| 58 | * - 32-bit virtual addressess
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| 59 | * - Offset is 12 bits => pages are 4K long
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| 60 | * - PTL0 has 1024 entries (10 bits)
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| 61 | * - PTL1 is not used
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| 62 | * - PTL2 is not used
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| 63 | * - PLT3 has 1024 entries (10 bits)
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| 64 | */
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[602c9101] | 65 |
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[c03ee1c] | 66 | /* Number of entries in each level. */
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[48c1ef9] | 67 | #define PTL0_ENTRIES_ARCH 1024
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| 68 | #define PTL1_ENTRIES_ARCH 0
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| 69 | #define PTL2_ENTRIES_ARCH 0
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| 70 | #define PTL3_ENTRIES_ARCH 1024
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[602c9101] | 71 |
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[c03ee1c] | 72 | /* Sizes of page tables in each level. */
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[6b781c0] | 73 | #define PTL0_SIZE_ARCH ONE_FRAME
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| 74 | #define PTL1_SIZE_ARCH 0
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| 75 | #define PTL2_SIZE_ARCH 0
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| 76 | #define PTL3_SIZE_ARCH ONE_FRAME
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| 77 |
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[c03ee1c] | 78 | /* Macros calculating indices into page tables in each level. */
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[48c1ef9] | 79 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff)
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| 80 | #define PTL1_INDEX_ARCH(vaddr) 0
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| 81 | #define PTL2_INDEX_ARCH(vaddr) 0
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| 82 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ff)
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[602c9101] | 83 |
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[c03ee1c] | 84 | /* Get PTE address accessors for each level. */
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| 85 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
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| 86 | (((pte_t *) (ptl0))[(i)].pfn << 12)
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| 87 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
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| 88 | (ptl1)
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| 89 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
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| 90 | (ptl2)
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| 91 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
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| 92 | (((pte_t *) (ptl3))[(i)].pfn << 12)
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| 93 |
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| 94 | /* Set PTE address accessors for each level. */
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[48c1ef9] | 95 | #define SET_PTL0_ADDRESS_ARCH(ptl0)
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[c03ee1c] | 96 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
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| 97 | (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12)
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[602c9101] | 98 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
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| 99 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
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[c03ee1c] | 100 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
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| 101 | (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12)
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| 102 |
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| 103 | /* Get PTE flags accessors for each level. */
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| 104 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) \
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| 105 | get_pt_flags((pte_t *) (ptl0), (index_t) (i))
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| 106 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) \
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| 107 | PAGE_PRESENT
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| 108 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) \
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| 109 | PAGE_PRESENT
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| 110 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) \
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| 111 | get_pt_flags((pte_t *) (ptl3), (index_t) (i))
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| 112 |
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| 113 | /* Set PTE flags accessors for each level. */
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| 114 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
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| 115 | set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
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[602c9101] | 116 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
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| 117 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
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[c03ee1c] | 118 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
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| 119 | set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
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[602c9101] | 120 |
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[c03ee1c] | 121 | /* Macros for querying the last-level PTEs. */
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[7f1c620] | 122 | #define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0)
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[fb84455] | 123 | #define PTE_PRESENT_ARCH(pte) ((pte)->p != 0)
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[7f1c620] | 124 | #define PTE_GET_FRAME_ARCH(pte) ((uintptr_t) ((pte)->pfn << 12))
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[fb84455] | 125 | #define PTE_WRITABLE_ARCH(pte) 1
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| 126 | #define PTE_EXECUTABLE_ARCH(pte) 1
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[602c9101] | 127 |
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| 128 | #ifndef __ASM__
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| 129 |
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[b3f8fb7] | 130 | #include <mm/mm.h>
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| 131 | #include <arch/interrupt.h>
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[602c9101] | 132 |
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[48c1ef9] | 133 | static inline int get_pt_flags(pte_t *pt, index_t i)
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| 134 | {
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| 135 | pte_t *p = &pt[i];
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| 136 |
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[c03ee1c] | 137 | return ((1 << PAGE_CACHEABLE_SHIFT) |
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| 138 | ((!p->p) << PAGE_PRESENT_SHIFT) |
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| 139 | (1 << PAGE_USER_SHIFT) |
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| 140 | (1 << PAGE_READ_SHIFT) |
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| 141 | (1 << PAGE_WRITE_SHIFT) |
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| 142 | (1 << PAGE_EXEC_SHIFT) |
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| 143 | (p->g << PAGE_GLOBAL_SHIFT));
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[48c1ef9] | 144 | }
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| 145 |
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| 146 | static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
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| 147 | {
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| 148 | pte_t *p = &pt[i];
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| 149 |
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| 150 | p->p = !(flags & PAGE_NOT_PRESENT);
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| 151 | p->g = (flags & PAGE_GLOBAL) != 0;
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| 152 | p->valid = 1;
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| 153 | }
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| 154 |
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[602c9101] | 155 | extern void page_arch_init(void);
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| 156 |
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[48c1ef9] | 157 | #define PHT_BITS 16
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| 158 | #define PHT_ORDER 4
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| 159 |
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| 160 | typedef struct {
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| 161 | unsigned v : 1; /**< Valid */
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| 162 | unsigned vsid : 24; /**< Virtual Segment ID */
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| 163 | unsigned h : 1; /**< Primary/secondary hash */
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| 164 | unsigned api : 6; /**< Abbreviated Page Index */
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| 165 | unsigned rpn : 20; /**< Real Page Number */
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| 166 | unsigned reserved0 : 3;
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| 167 | unsigned r : 1; /**< Reference */
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| 168 | unsigned c : 1; /**< Change */
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| 169 | unsigned wimg : 4; /**< Access control */
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| 170 | unsigned reserved1 : 1;
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| 171 | unsigned pp : 2; /**< Page protection */
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| 172 | } phte_t;
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| 173 |
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| 174 | extern void pht_refill(bool data, istate_t *istate);
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| 175 | extern void pht_init(void);
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| 176 |
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[602c9101] | 177 | #endif /* __ASM__ */
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| 178 |
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| 179 | #endif /* KERNEL */
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| 180 |
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| 181 | #endif
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[b45c443] | 182 |
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[06e1e95] | 183 | /** @}
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[b45c443] | 184 | */
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