| 1 | /*
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| 2 | * Copyright (c) 2005 Martin Decky
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 |
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| 30 | #include <barrier.h>
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| 31 |
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| 32 | #define COHERENCE_INVAL_MIN 4
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| 33 |
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| 34 | /*
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| 35 | * The IMB sequence used here is valid for all possible cache models
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| 36 | * on uniprocessor. SMP might require a different sequence.
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| 37 | * See PowerPC Programming Environment for 32-Bit Microprocessors,
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| 38 | * chapter 5.1.5.2
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| 39 | */
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| 40 |
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| 41 | void smc_coherence(void *addr, size_t len)
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| 42 | {
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| 43 | unsigned int i;
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| 44 |
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| 45 | for (i = 0; i < len; i += COHERENCE_INVAL_MIN)
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| 46 | asm volatile (
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| 47 | "dcbst 0, %[addr]\n"
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| 48 | :: [addr] "r" (addr + i)
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| 49 | );
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| 50 |
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| 51 | asm volatile ("sync" ::: "memory");
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| 52 |
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| 53 | for (i = 0; i < len; i += COHERENCE_INVAL_MIN)
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| 54 | asm volatile (
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| 55 | "icbi 0, %[addr]\n"
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| 56 | :: [addr] "r" (addr + i)
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| 57 | );
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| 58 |
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| 59 | asm volatile ("sync" ::: "memory");
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| 60 | asm volatile ("isync" ::: "memory");
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| 61 | }
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| 62 |
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