source: mainline/kernel/arch/ppc32/src/mm/tlb.c@ 77385fe

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 77385fe was 5b8016d, checked in by Jakub Jermar <jakub@…>, 15 years ago

Switch ppc32 to use the unified panic architecture. Untested as ppc32 does not boot.
  • Property mode set to 100644
File size: 11.1 KB
Line 
1/*
2 * Copyright (c) 2006 Martin Decky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ppc32mm
30 * @{
31 */
32/** @file
33 */
34
35#include <mm/tlb.h>
36#include <arch/mm/tlb.h>
37#include <arch/interrupt.h>
38#include <interrupt.h>
39#include <mm/as.h>
40#include <mm/page.h>
41#include <arch.h>
42#include <print.h>
43#include <macros.h>
44#include <symtab.h>
45
46static unsigned int seed = 10;
47static unsigned int seed_real
48 __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42;
49
50/** Try to find PTE for faulting address
51 *
52 * @param as Address space.
53 * @param lock Lock/unlock the address space.
54 * @param badvaddr Faulting virtual address.
55 * @param access Access mode that caused the fault.
56 * @param istate Pointer to interrupted state.
57 * @param pfrc Pointer to variable where as_page_fault() return code
58 * will be stored.
59 *
60 * @return PTE on success, NULL otherwise.
61 *
62 */
63static pte_t *find_mapping_and_check(as_t *as, uintptr_t badvaddr, int access,
64 istate_t *istate, int *pfrc)
65{
66 ASSERT(mutex_locked(&as->lock));
67
68 /*
69 * Check if the mapping exists in page tables.
70 */
71 pte_t *pte = page_mapping_find(as, badvaddr);
72 if ((pte) && (pte->present)) {
73 /*
74 * Mapping found in page tables.
75 * Immediately succeed.
76 */
77 return pte;
78 } else {
79 /*
80 * Mapping not found in page tables.
81 * Resort to higher-level page fault handler.
82 */
83 page_table_unlock(as, true);
84
85 int rc = as_page_fault(badvaddr, access, istate);
86 switch (rc) {
87 case AS_PF_OK:
88 /*
89 * The higher-level page fault handler succeeded,
90 * The mapping ought to be in place.
91 */
92 page_table_lock(as, true);
93 pte = page_mapping_find(as, badvaddr);
94 ASSERT((pte) && (pte->present));
95 *pfrc = 0;
96 return pte;
97 case AS_PF_DEFER:
98 page_table_lock(as, true);
99 *pfrc = rc;
100 return NULL;
101 case AS_PF_FAULT:
102 page_table_lock(as, true);
103 *pfrc = rc;
104 return NULL;
105 default:
106 panic("Unexpected rc (%d).", rc);
107 }
108 }
109}
110
111static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
112{
113 fault_if_from_uspace(istate, "PHT Refill Exception on %p.", badvaddr);
114 panic_memtrap(istate, PF_ACCESS_READ, badvaddr,
115 "PHT Refill Exception.");
116}
117
118static void pht_insert(const uintptr_t vaddr, const pte_t *pte)
119{
120 uint32_t page = (vaddr >> 12) & 0xffff;
121 uint32_t api = (vaddr >> 22) & 0x3f;
122
123 uint32_t vsid = sr_get(vaddr);
124 uint32_t sdr1 = sdr1_get();
125
126 // FIXME: compute size of PHT exactly
127 phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
128
129 /* Primary hash (xor) */
130 uint32_t h = 0;
131 uint32_t hash = vsid ^ page;
132 uint32_t base = (hash & 0x3ff) << 3;
133 uint32_t i;
134 bool found = false;
135
136 /* Find colliding PTE in PTEG */
137 for (i = 0; i < 8; i++) {
138 if ((phte[base + i].v)
139 && (phte[base + i].vsid == vsid)
140 && (phte[base + i].api == api)
141 && (phte[base + i].h == 0)) {
142 found = true;
143 break;
144 }
145 }
146
147 if (!found) {
148 /* Find unused PTE in PTEG */
149 for (i = 0; i < 8; i++) {
150 if (!phte[base + i].v) {
151 found = true;
152 break;
153 }
154 }
155 }
156
157 if (!found) {
158 /* Secondary hash (not) */
159 uint32_t base2 = (~hash & 0x3ff) << 3;
160
161 /* Find colliding PTE in PTEG */
162 for (i = 0; i < 8; i++) {
163 if ((phte[base2 + i].v)
164 && (phte[base2 + i].vsid == vsid)
165 && (phte[base2 + i].api == api)
166 && (phte[base2 + i].h == 1)) {
167 found = true;
168 base = base2;
169 h = 1;
170 break;
171 }
172 }
173
174 if (!found) {
175 /* Find unused PTE in PTEG */
176 for (i = 0; i < 8; i++) {
177 if (!phte[base2 + i].v) {
178 found = true;
179 base = base2;
180 h = 1;
181 break;
182 }
183 }
184 }
185
186 if (!found)
187 i = RANDI(seed) % 8;
188 }
189
190 phte[base + i].v = 1;
191 phte[base + i].vsid = vsid;
192 phte[base + i].h = h;
193 phte[base + i].api = api;
194 phte[base + i].rpn = pte->pfn;
195 phte[base + i].r = 0;
196 phte[base + i].c = 0;
197 phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0);
198 phte[base + i].pp = 2; // FIXME
199}
200
201/** Process Instruction/Data Storage Exception
202 *
203 * @param n Exception vector number.
204 * @param istate Interrupted register context.
205 *
206 */
207void pht_refill(unsigned int n, istate_t *istate)
208{
209 as_t *as = (AS == NULL) ? AS_KERNEL : AS;
210 uintptr_t badvaddr;
211
212 if (n == VECTOR_DATA_STORAGE)
213 badvaddr = istate->dar;
214 else
215 badvaddr = istate->pc;
216
217 page_table_lock(as, true);
218
219 int pfrc;
220 pte_t *pte = find_mapping_and_check(as, badvaddr,
221 PF_ACCESS_READ /* FIXME */, istate, &pfrc);
222
223 if (!pte) {
224 switch (pfrc) {
225 case AS_PF_FAULT:
226 goto fail;
227 break;
228 case AS_PF_DEFER:
229 /*
230 * The page fault came during copy_from_uspace()
231 * or copy_to_uspace().
232 */
233 page_table_unlock(as, true);
234 return;
235 default:
236 panic("Unexpected pfrc (%d).", pfrc);
237 }
238 }
239
240 /* Record access to PTE */
241 pte->accessed = 1;
242 pht_insert(badvaddr, pte);
243
244 page_table_unlock(as, true);
245 return;
246
247fail:
248 page_table_unlock(as, true);
249 pht_refill_fail(badvaddr, istate);
250}
251
252/** Process Instruction/Data Storage Exception in Real Mode
253 *
254 * @param n Exception vector number.
255 * @param istate Interrupted register context.
256 *
257 */
258bool pht_refill_real(unsigned int n, istate_t *istate)
259{
260 uintptr_t badvaddr;
261
262 if (n == VECTOR_DATA_STORAGE)
263 badvaddr = istate->dar;
264 else
265 badvaddr = istate->pc;
266
267 uint32_t physmem = physmem_top();
268
269 if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem)))
270 return false;
271
272 uint32_t page = (badvaddr >> 12) & 0xffff;
273 uint32_t api = (badvaddr >> 22) & 0x3f;
274
275 uint32_t vsid = sr_get(badvaddr);
276 uint32_t sdr1 = sdr1_get();
277
278 // FIXME: compute size of PHT exactly
279 phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000);
280
281 /* Primary hash (xor) */
282 uint32_t h = 0;
283 uint32_t hash = vsid ^ page;
284 uint32_t base = (hash & 0x3ff) << 3;
285 uint32_t i;
286 bool found = false;
287
288 /* Find colliding PTE in PTEG */
289 for (i = 0; i < 8; i++) {
290 if ((phte_real[base + i].v)
291 && (phte_real[base + i].vsid == vsid)
292 && (phte_real[base + i].api == api)
293 && (phte_real[base + i].h == 0)) {
294 found = true;
295 break;
296 }
297 }
298
299 if (!found) {
300 /* Find unused PTE in PTEG */
301 for (i = 0; i < 8; i++) {
302 if (!phte_real[base + i].v) {
303 found = true;
304 break;
305 }
306 }
307 }
308
309 if (!found) {
310 /* Secondary hash (not) */
311 uint32_t base2 = (~hash & 0x3ff) << 3;
312
313 /* Find colliding PTE in PTEG */
314 for (i = 0; i < 8; i++) {
315 if ((phte_real[base2 + i].v)
316 && (phte_real[base2 + i].vsid == vsid)
317 && (phte_real[base2 + i].api == api)
318 && (phte_real[base2 + i].h == 1)) {
319 found = true;
320 base = base2;
321 h = 1;
322 break;
323 }
324 }
325
326 if (!found) {
327 /* Find unused PTE in PTEG */
328 for (i = 0; i < 8; i++) {
329 if (!phte_real[base2 + i].v) {
330 found = true;
331 base = base2;
332 h = 1;
333 break;
334 }
335 }
336 }
337
338 if (!found) {
339 /* Use secondary hash to avoid collisions
340 with usual PHT refill handler. */
341 i = RANDI(seed_real) % 8;
342 base = base2;
343 h = 1;
344 }
345 }
346
347 phte_real[base + i].v = 1;
348 phte_real[base + i].vsid = vsid;
349 phte_real[base + i].h = h;
350 phte_real[base + i].api = api;
351 phte_real[base + i].rpn = KA2PA(badvaddr) >> 12;
352 phte_real[base + i].r = 0;
353 phte_real[base + i].c = 0;
354 phte_real[base + i].wimg = 0;
355 phte_real[base + i].pp = 2; // FIXME
356
357 return true;
358}
359
360/** Process ITLB/DTLB Miss Exception in Real Mode
361 *
362 *
363 */
364void tlb_refill_real(unsigned int n, uint32_t tlbmiss, ptehi_t ptehi,
365 ptelo_t ptelo, istate_t *istate)
366{
367 uint32_t badvaddr = tlbmiss & 0xfffffffc;
368 uint32_t physmem = physmem_top();
369
370 if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem)))
371 return; // FIXME
372
373 ptelo.rpn = KA2PA(badvaddr) >> 12;
374 ptelo.wimg = 0;
375 ptelo.pp = 2; // FIXME
376
377 uint32_t index = 0;
378 asm volatile (
379 "mtspr 981, %[ptehi]\n"
380 "mtspr 982, %[ptelo]\n"
381 "tlbld %[index]\n"
382 "tlbli %[index]\n"
383 : [index] "=r" (index)
384 : [ptehi] "r" (ptehi),
385 [ptelo] "r" (ptelo)
386 );
387}
388
389void tlb_arch_init(void)
390{
391 tlb_invalidate_all();
392}
393
394void tlb_invalidate_all(void)
395{
396 uint32_t index;
397
398 asm volatile (
399 "li %[index], 0\n"
400 "sync\n"
401
402 ".rept 64\n"
403 " tlbie %[index]\n"
404 " addi %[index], %[index], 0x1000\n"
405 ".endr\n"
406
407 "eieio\n"
408 "tlbsync\n"
409 "sync\n"
410 : [index] "=r" (index)
411 );
412}
413
414void tlb_invalidate_asid(asid_t asid)
415{
416 uint32_t sdr1 = sdr1_get();
417
418 // FIXME: compute size of PHT exactly
419 phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
420
421 size_t i;
422 for (i = 0; i < 8192; i++) {
423 if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) &&
424 (phte[i].vsid < ((asid << 4) + 16)))
425 phte[i].v = 0;
426 }
427
428 tlb_invalidate_all();
429}
430
431void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
432{
433 // TODO
434 tlb_invalidate_all();
435}
436
437#define PRINT_BAT(name, ureg, lreg) \
438 asm volatile ( \
439 "mfspr %[upper], " #ureg "\n" \
440 "mfspr %[lower], " #lreg "\n" \
441 : [upper] "=r" (upper), \
442 [lower] "=r" (lower) \
443 ); \
444 \
445 mask = (upper & 0x1ffc) >> 2; \
446 if (upper & 3) { \
447 uint32_t tmp = mask; \
448 length = 128; \
449 \
450 while (tmp) { \
451 if ((tmp & 1) == 0) { \
452 printf("ibat[0]: error in mask\n"); \
453 break; \
454 } \
455 length <<= 1; \
456 tmp >>= 1; \
457 } \
458 } else \
459 length = 0; \
460 \
461 printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \
462 sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \
463 lower & 0xffff0000, length, mask, \
464 ((upper >> 1) & 1) ? " supervisor" : "", \
465 (upper & 1) ? " user" : "");
466
467
468void tlb_print(void)
469{
470 uint32_t sr;
471
472 for (sr = 0; sr < 16; sr++) {
473 uint32_t vsid = sr_get(sr << 28);
474
475 printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr,
476 sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,
477 ((vsid >> 30) & 1) ? " supervisor" : "",
478 ((vsid >> 29) & 1) ? " user" : "");
479 }
480
481 uint32_t upper;
482 uint32_t lower;
483 uint32_t mask;
484 uint32_t length;
485
486 PRINT_BAT("ibat[0]", 528, 529);
487 PRINT_BAT("ibat[1]", 530, 531);
488 PRINT_BAT("ibat[2]", 532, 533);
489 PRINT_BAT("ibat[3]", 534, 535);
490
491 PRINT_BAT("dbat[0]", 536, 537);
492 PRINT_BAT("dbat[1]", 538, 539);
493 PRINT_BAT("dbat[2]", 540, 541);
494 PRINT_BAT("dbat[3]", 542, 543);
495}
496
497/** @}
498 */
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