source: mainline/kernel/arch/ppc32/src/mm/tlb.c@ 5954241

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 5954241 was 5954241, checked in by Martin Decky <martin@…>, 15 years ago

fix exception handler prototypes
  • Property mode set to 100644
File size: 11.2 KB
Line 
1/*
2 * Copyright (c) 2006 Martin Decky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ppc32mm
30 * @{
31 */
32/** @file
33 */
34
35#include <mm/tlb.h>
36#include <arch/mm/tlb.h>
37#include <arch/interrupt.h>
38#include <interrupt.h>
39#include <mm/as.h>
40#include <mm/page.h>
41#include <arch.h>
42#include <print.h>
43#include <macros.h>
44#include <symtab.h>
45
46static unsigned int seed = 10;
47static unsigned int seed_real
48 __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42;
49
50/** Try to find PTE for faulting address
51 *
52 * @param as Address space.
53 * @param lock Lock/unlock the address space.
54 * @param badvaddr Faulting virtual address.
55 * @param access Access mode that caused the fault.
56 * @param istate Pointer to interrupted state.
57 * @param pfrc Pointer to variable where as_page_fault() return code
58 * will be stored.
59 *
60 * @return PTE on success, NULL otherwise.
61 *
62 */
63static pte_t *find_mapping_and_check(as_t *as, uintptr_t badvaddr, int access,
64 istate_t *istate, int *pfrc)
65{
66 ASSERT(mutex_locked(&as->lock));
67
68 /*
69 * Check if the mapping exists in page tables.
70 */
71 pte_t *pte = page_mapping_find(as, badvaddr);
72 if ((pte) && (pte->present)) {
73 /*
74 * Mapping found in page tables.
75 * Immediately succeed.
76 */
77 return pte;
78 } else {
79 /*
80 * Mapping not found in page tables.
81 * Resort to higher-level page fault handler.
82 */
83 page_table_unlock(as, true);
84
85 int rc = as_page_fault(badvaddr, access, istate);
86 switch (rc) {
87 case AS_PF_OK:
88 /*
89 * The higher-level page fault handler succeeded,
90 * The mapping ought to be in place.
91 */
92 page_table_lock(as, true);
93 pte = page_mapping_find(as, badvaddr);
94 ASSERT((pte) && (pte->present));
95 *pfrc = 0;
96 return pte;
97 case AS_PF_DEFER:
98 page_table_lock(as, true);
99 *pfrc = rc;
100 return NULL;
101 case AS_PF_FAULT:
102 page_table_lock(as, true);
103 *pfrc = rc;
104 return NULL;
105 default:
106 panic("Unexpected rc (%d).", rc);
107 }
108 }
109}
110
111static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
112{
113 const char *symbol = symtab_fmt_name_lookup(istate->pc);
114 const char *sym2 = symtab_fmt_name_lookup(istate->lr);
115
116 fault_if_from_uspace(istate,
117 "PHT Refill Exception on %p.", badvaddr);
118 panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr,
119 istate->pc, symbol, sym2);
120}
121
122static void pht_insert(const uintptr_t vaddr, const pte_t *pte)
123{
124 uint32_t page = (vaddr >> 12) & 0xffff;
125 uint32_t api = (vaddr >> 22) & 0x3f;
126
127 uint32_t vsid = sr_get(vaddr);
128 uint32_t sdr1 = sdr1_get();
129
130 // FIXME: compute size of PHT exactly
131 phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
132
133 /* Primary hash (xor) */
134 uint32_t h = 0;
135 uint32_t hash = vsid ^ page;
136 uint32_t base = (hash & 0x3ff) << 3;
137 uint32_t i;
138 bool found = false;
139
140 /* Find colliding PTE in PTEG */
141 for (i = 0; i < 8; i++) {
142 if ((phte[base + i].v)
143 && (phte[base + i].vsid == vsid)
144 && (phte[base + i].api == api)
145 && (phte[base + i].h == 0)) {
146 found = true;
147 break;
148 }
149 }
150
151 if (!found) {
152 /* Find unused PTE in PTEG */
153 for (i = 0; i < 8; i++) {
154 if (!phte[base + i].v) {
155 found = true;
156 break;
157 }
158 }
159 }
160
161 if (!found) {
162 /* Secondary hash (not) */
163 uint32_t base2 = (~hash & 0x3ff) << 3;
164
165 /* Find colliding PTE in PTEG */
166 for (i = 0; i < 8; i++) {
167 if ((phte[base2 + i].v)
168 && (phte[base2 + i].vsid == vsid)
169 && (phte[base2 + i].api == api)
170 && (phte[base2 + i].h == 1)) {
171 found = true;
172 base = base2;
173 h = 1;
174 break;
175 }
176 }
177
178 if (!found) {
179 /* Find unused PTE in PTEG */
180 for (i = 0; i < 8; i++) {
181 if (!phte[base2 + i].v) {
182 found = true;
183 base = base2;
184 h = 1;
185 break;
186 }
187 }
188 }
189
190 if (!found)
191 i = RANDI(seed) % 8;
192 }
193
194 phte[base + i].v = 1;
195 phte[base + i].vsid = vsid;
196 phte[base + i].h = h;
197 phte[base + i].api = api;
198 phte[base + i].rpn = pte->pfn;
199 phte[base + i].r = 0;
200 phte[base + i].c = 0;
201 phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0);
202 phte[base + i].pp = 2; // FIXME
203}
204
205/** Process Instruction/Data Storage Exception
206 *
207 * @param n Exception vector number.
208 * @param istate Interrupted register context.
209 *
210 */
211void pht_refill(unsigned int n, istate_t *istate)
212{
213 as_t *as = (AS == NULL) ? AS_KERNEL : AS;
214 uintptr_t badvaddr;
215
216 if (n == VECTOR_DATA_STORAGE)
217 badvaddr = istate->dar;
218 else
219 badvaddr = istate->pc;
220
221 page_table_lock(as, true);
222
223 int pfrc;
224 pte_t *pte = find_mapping_and_check(as, badvaddr,
225 PF_ACCESS_READ /* FIXME */, istate, &pfrc);
226
227 if (!pte) {
228 switch (pfrc) {
229 case AS_PF_FAULT:
230 goto fail;
231 break;
232 case AS_PF_DEFER:
233 /*
234 * The page fault came during copy_from_uspace()
235 * or copy_to_uspace().
236 */
237 page_table_unlock(as, true);
238 return;
239 default:
240 panic("Unexpected pfrc (%d).", pfrc);
241 }
242 }
243
244 /* Record access to PTE */
245 pte->accessed = 1;
246 pht_insert(badvaddr, pte);
247
248 page_table_unlock(as, true);
249 return;
250
251fail:
252 page_table_unlock(as, true);
253 pht_refill_fail(badvaddr, istate);
254}
255
256/** Process Instruction/Data Storage Exception in Real Mode
257 *
258 * @param n Exception vector number.
259 * @param istate Interrupted register context.
260 *
261 */
262bool pht_refill_real(unsigned int n, istate_t *istate)
263{
264 uintptr_t badvaddr;
265
266 if (n == VECTOR_DATA_STORAGE)
267 badvaddr = istate->dar;
268 else
269 badvaddr = istate->pc;
270
271 uint32_t physmem = physmem_top();
272
273 if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem)))
274 return false;
275
276 uint32_t page = (badvaddr >> 12) & 0xffff;
277 uint32_t api = (badvaddr >> 22) & 0x3f;
278
279 uint32_t vsid = sr_get(badvaddr);
280 uint32_t sdr1 = sdr1_get();
281
282 // FIXME: compute size of PHT exactly
283 phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000);
284
285 /* Primary hash (xor) */
286 uint32_t h = 0;
287 uint32_t hash = vsid ^ page;
288 uint32_t base = (hash & 0x3ff) << 3;
289 uint32_t i;
290 bool found = false;
291
292 /* Find colliding PTE in PTEG */
293 for (i = 0; i < 8; i++) {
294 if ((phte_real[base + i].v)
295 && (phte_real[base + i].vsid == vsid)
296 && (phte_real[base + i].api == api)
297 && (phte_real[base + i].h == 0)) {
298 found = true;
299 break;
300 }
301 }
302
303 if (!found) {
304 /* Find unused PTE in PTEG */
305 for (i = 0; i < 8; i++) {
306 if (!phte_real[base + i].v) {
307 found = true;
308 break;
309 }
310 }
311 }
312
313 if (!found) {
314 /* Secondary hash (not) */
315 uint32_t base2 = (~hash & 0x3ff) << 3;
316
317 /* Find colliding PTE in PTEG */
318 for (i = 0; i < 8; i++) {
319 if ((phte_real[base2 + i].v)
320 && (phte_real[base2 + i].vsid == vsid)
321 && (phte_real[base2 + i].api == api)
322 && (phte_real[base2 + i].h == 1)) {
323 found = true;
324 base = base2;
325 h = 1;
326 break;
327 }
328 }
329
330 if (!found) {
331 /* Find unused PTE in PTEG */
332 for (i = 0; i < 8; i++) {
333 if (!phte_real[base2 + i].v) {
334 found = true;
335 base = base2;
336 h = 1;
337 break;
338 }
339 }
340 }
341
342 if (!found) {
343 /* Use secondary hash to avoid collisions
344 with usual PHT refill handler. */
345 i = RANDI(seed_real) % 8;
346 base = base2;
347 h = 1;
348 }
349 }
350
351 phte_real[base + i].v = 1;
352 phte_real[base + i].vsid = vsid;
353 phte_real[base + i].h = h;
354 phte_real[base + i].api = api;
355 phte_real[base + i].rpn = KA2PA(badvaddr) >> 12;
356 phte_real[base + i].r = 0;
357 phte_real[base + i].c = 0;
358 phte_real[base + i].wimg = 0;
359 phte_real[base + i].pp = 2; // FIXME
360
361 return true;
362}
363
364/** Process ITLB/DTLB Miss Exception in Real Mode
365 *
366 *
367 */
368void tlb_refill_real(unsigned int n, uint32_t tlbmiss, ptehi_t ptehi,
369 ptelo_t ptelo, istate_t *istate)
370{
371 uint32_t badvaddr = tlbmiss & 0xfffffffc;
372 uint32_t physmem = physmem_top();
373
374 if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem)))
375 return; // FIXME
376
377 ptelo.rpn = KA2PA(badvaddr) >> 12;
378 ptelo.wimg = 0;
379 ptelo.pp = 2; // FIXME
380
381 uint32_t index = 0;
382 asm volatile (
383 "mtspr 981, %[ptehi]\n"
384 "mtspr 982, %[ptelo]\n"
385 "tlbld %[index]\n"
386 "tlbli %[index]\n"
387 : [index] "=r" (index)
388 : [ptehi] "r" (ptehi),
389 [ptelo] "r" (ptelo)
390 );
391}
392
393void tlb_arch_init(void)
394{
395 tlb_invalidate_all();
396}
397
398void tlb_invalidate_all(void)
399{
400 uint32_t index;
401
402 asm volatile (
403 "li %[index], 0\n"
404 "sync\n"
405
406 ".rept 64\n"
407 " tlbie %[index]\n"
408 " addi %[index], %[index], 0x1000\n"
409 ".endr\n"
410
411 "eieio\n"
412 "tlbsync\n"
413 "sync\n"
414 : [index] "=r" (index)
415 );
416}
417
418void tlb_invalidate_asid(asid_t asid)
419{
420 uint32_t sdr1 = sdr1_get();
421
422 // FIXME: compute size of PHT exactly
423 phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
424
425 size_t i;
426 for (i = 0; i < 8192; i++) {
427 if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) &&
428 (phte[i].vsid < ((asid << 4) + 16)))
429 phte[i].v = 0;
430 }
431
432 tlb_invalidate_all();
433}
434
435void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
436{
437 // TODO
438 tlb_invalidate_all();
439}
440
441#define PRINT_BAT(name, ureg, lreg) \
442 asm volatile ( \
443 "mfspr %[upper], " #ureg "\n" \
444 "mfspr %[lower], " #lreg "\n" \
445 : [upper] "=r" (upper), \
446 [lower] "=r" (lower) \
447 ); \
448 \
449 mask = (upper & 0x1ffc) >> 2; \
450 if (upper & 3) { \
451 uint32_t tmp = mask; \
452 length = 128; \
453 \
454 while (tmp) { \
455 if ((tmp & 1) == 0) { \
456 printf("ibat[0]: error in mask\n"); \
457 break; \
458 } \
459 length <<= 1; \
460 tmp >>= 1; \
461 } \
462 } else \
463 length = 0; \
464 \
465 printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \
466 sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \
467 lower & 0xffff0000, length, mask, \
468 ((upper >> 1) & 1) ? " supervisor" : "", \
469 (upper & 1) ? " user" : "");
470
471
472void tlb_print(void)
473{
474 uint32_t sr;
475
476 for (sr = 0; sr < 16; sr++) {
477 uint32_t vsid = sr_get(sr << 28);
478
479 printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr,
480 sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,
481 ((vsid >> 30) & 1) ? " supervisor" : "",
482 ((vsid >> 29) & 1) ? " user" : "");
483 }
484
485 uint32_t upper;
486 uint32_t lower;
487 uint32_t mask;
488 uint32_t length;
489
490 PRINT_BAT("ibat[0]", 528, 529);
491 PRINT_BAT("ibat[1]", 530, 531);
492 PRINT_BAT("ibat[2]", 532, 533);
493 PRINT_BAT("ibat[3]", 534, 535);
494
495 PRINT_BAT("dbat[0]", 536, 537);
496 PRINT_BAT("dbat[1]", 538, 539);
497 PRINT_BAT("dbat[2]", 540, 541);
498 PRINT_BAT("dbat[3]", 542, 543);
499}
500
501/** @}
502 */
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