source: mainline/kernel/arch/ppc32/src/mm/tlb.c@ 77385fe

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 77385fe was 5b8016d, checked in by Jakub Jermar <jakub@…>, 15 years ago

Switch ppc32 to use the unified panic architecture. Untested as ppc32 does not boot.
  • Property mode set to 100644
File size: 11.1 KB
RevLine 
[613bc54]1/*
[df4ed85]2 * Copyright (c) 2006 Martin Decky
[613bc54]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[7b187ef]29/** @addtogroup ppc32mm
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[613bc54]35#include <mm/tlb.h>
[10e0cee]36#include <arch/mm/tlb.h>
37#include <arch/interrupt.h>
[26fa0f9f]38#include <interrupt.h>
[10e0cee]39#include <mm/as.h>
[eae4e8f]40#include <mm/page.h>
[10e0cee]41#include <arch.h>
42#include <print.h>
[53634f9]43#include <macros.h>
[e2b762ec]44#include <symtab.h>
[9a68b34d]45
[896ad9f]46static unsigned int seed = 10;
[da1bafb]47static unsigned int seed_real
48 __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42;
[896ad9f]49
[10e0cee]50/** Try to find PTE for faulting address
51 *
[da1bafb]52 * @param as Address space.
53 * @param lock Lock/unlock the address space.
54 * @param badvaddr Faulting virtual address.
55 * @param access Access mode that caused the fault.
56 * @param istate Pointer to interrupted state.
57 * @param pfrc Pointer to variable where as_page_fault() return code
58 * will be stored.
59 *
60 * @return PTE on success, NULL otherwise.
[613bc54]61 *
62 */
[a820bf7]63static pte_t *find_mapping_and_check(as_t *as, uintptr_t badvaddr, int access,
64 istate_t *istate, int *pfrc)
[10e0cee]65{
[1d432f9]66 ASSERT(mutex_locked(&as->lock));
67
[10e0cee]68 /*
69 * Check if the mapping exists in page tables.
[da1bafb]70 */
[10e0cee]71 pte_t *pte = page_mapping_find(as, badvaddr);
[43d6401]72 if ((pte) && (pte->present)) {
[10e0cee]73 /*
74 * Mapping found in page tables.
75 * Immediately succeed.
76 */
77 return pte;
78 } else {
79 /*
80 * Mapping not found in page tables.
81 * Resort to higher-level page fault handler.
82 */
[a820bf7]83 page_table_unlock(as, true);
[da1bafb]84
85 int rc = as_page_fault(badvaddr, access, istate);
86 switch (rc) {
[5d67baa]87 case AS_PF_OK:
88 /*
89 * The higher-level page fault handler succeeded,
90 * The mapping ought to be in place.
91 */
[a820bf7]92 page_table_lock(as, true);
[5d67baa]93 pte = page_mapping_find(as, badvaddr);
[43d6401]94 ASSERT((pte) && (pte->present));
[5d67baa]95 *pfrc = 0;
96 return pte;
97 case AS_PF_DEFER:
[a820bf7]98 page_table_lock(as, true);
[5d67baa]99 *pfrc = rc;
100 return NULL;
101 case AS_PF_FAULT:
[a820bf7]102 page_table_lock(as, true);
[5d67baa]103 *pfrc = rc;
104 return NULL;
105 default:
[f651e80]106 panic("Unexpected rc (%d).", rc);
[da1bafb]107 }
[10e0cee]108 }
109}
110
[7f1c620]111static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
[10e0cee]112{
[5b8016d]113 fault_if_from_uspace(istate, "PHT Refill Exception on %p.", badvaddr);
114 panic_memtrap(istate, PF_ACCESS_READ, badvaddr,
115 "PHT Refill Exception.");
[10e0cee]116}
117
[43d6401]118static void pht_insert(const uintptr_t vaddr, const pte_t *pte)
[10e0cee]119{
[7f1c620]120 uint32_t page = (vaddr >> 12) & 0xffff;
121 uint32_t api = (vaddr >> 22) & 0x3f;
[10e0cee]122
[da1bafb]123 uint32_t vsid = sr_get(vaddr);
124 uint32_t sdr1 = sdr1_get();
[10e0cee]125
[da1bafb]126 // FIXME: compute size of PHT exactly
[10e0cee]127 phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
128
129 /* Primary hash (xor) */
[7f1c620]130 uint32_t h = 0;
131 uint32_t hash = vsid ^ page;
132 uint32_t base = (hash & 0x3ff) << 3;
133 uint32_t i;
[10e0cee]134 bool found = false;
135
[1e241723]136 /* Find colliding PTE in PTEG */
[10e0cee]137 for (i = 0; i < 8; i++) {
[1e241723]138 if ((phte[base + i].v)
139 && (phte[base + i].vsid == vsid)
[7c98874]140 && (phte[base + i].api == api)
[1e241723]141 && (phte[base + i].h == 0)) {
[10e0cee]142 found = true;
143 break;
144 }
145 }
146
[1e241723]147 if (!found) {
148 /* Find unused PTE in PTEG */
149 for (i = 0; i < 8; i++) {
150 if (!phte[base + i].v) {
151 found = true;
152 break;
153 }
154 }
155 }
156
[10e0cee]157 if (!found) {
158 /* Secondary hash (not) */
[7f1c620]159 uint32_t base2 = (~hash & 0x3ff) << 3;
[10e0cee]160
[1e241723]161 /* Find colliding PTE in PTEG */
[10e0cee]162 for (i = 0; i < 8; i++) {
[1e241723]163 if ((phte[base2 + i].v)
164 && (phte[base2 + i].vsid == vsid)
[7c98874]165 && (phte[base2 + i].api == api)
[1e241723]166 && (phte[base2 + i].h == 1)) {
[10e0cee]167 found = true;
168 base = base2;
169 h = 1;
170 break;
171 }
172 }
173
[1e241723]174 if (!found) {
175 /* Find unused PTE in PTEG */
176 for (i = 0; i < 8; i++) {
177 if (!phte[base2 + i].v) {
178 found = true;
179 base = base2;
180 h = 1;
181 break;
182 }
183 }
184 }
185
[7c98874]186 if (!found)
[896ad9f]187 i = RANDI(seed) % 8;
[10e0cee]188 }
189
190 phte[base + i].v = 1;
191 phte[base + i].vsid = vsid;
192 phte[base + i].h = h;
193 phte[base + i].api = api;
[43d6401]194 phte[base + i].rpn = pte->pfn;
[10e0cee]195 phte[base + i].r = 0;
196 phte[base + i].c = 0;
[43d6401]197 phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0);
[10e0cee]198 phte[base + i].pp = 2; // FIXME
199}
200
[0867321]201/** Process Instruction/Data Storage Exception
[10e0cee]202 *
[0867321]203 * @param n Exception vector number.
204 * @param istate Interrupted register context.
[10e0cee]205 *
206 */
[5954241]207void pht_refill(unsigned int n, istate_t *istate)
[10e0cee]208{
[a820bf7]209 as_t *as = (AS == NULL) ? AS_KERNEL : AS;
[da1bafb]210 uintptr_t badvaddr;
211
[826c203]212 if (n == VECTOR_DATA_STORAGE)
213 badvaddr = istate->dar;
214 else
[10e0cee]215 badvaddr = istate->pc;
[da1bafb]216
[a820bf7]217 page_table_lock(as, true);
[10e0cee]218
[da1bafb]219 int pfrc;
[a820bf7]220 pte_t *pte = find_mapping_and_check(as, badvaddr,
[5d67baa]221 PF_ACCESS_READ /* FIXME */, istate, &pfrc);
[da1bafb]222
[10e0cee]223 if (!pte) {
224 switch (pfrc) {
[5d67baa]225 case AS_PF_FAULT:
226 goto fail;
227 break;
228 case AS_PF_DEFER:
229 /*
230 * The page fault came during copy_from_uspace()
231 * or copy_to_uspace().
232 */
[a820bf7]233 page_table_unlock(as, true);
[5d67baa]234 return;
235 default:
[f651e80]236 panic("Unexpected pfrc (%d).", pfrc);
[10e0cee]237 }
238 }
239
[da1bafb]240 /* Record access to PTE */
241 pte->accessed = 1;
[43d6401]242 pht_insert(badvaddr, pte);
[10e0cee]243
[a820bf7]244 page_table_unlock(as, true);
[10e0cee]245 return;
246
247fail:
[a820bf7]248 page_table_unlock(as, true);
[10e0cee]249 pht_refill_fail(badvaddr, istate);
250}
251
[0867321]252/** Process Instruction/Data Storage Exception in Real Mode
[10e0cee]253 *
[0867321]254 * @param n Exception vector number.
255 * @param istate Interrupted register context.
[10e0cee]256 *
257 */
[5954241]258bool pht_refill_real(unsigned int n, istate_t *istate)
[10e0cee]259{
[7f1c620]260 uintptr_t badvaddr;
[10e0cee]261
[826c203]262 if (n == VECTOR_DATA_STORAGE)
263 badvaddr = istate->dar;
264 else
[10e0cee]265 badvaddr = istate->pc;
266
[da1bafb]267 uint32_t physmem = physmem_top();
[10e0cee]268
[896ad9f]269 if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem)))
270 return false;
271
272 uint32_t page = (badvaddr >> 12) & 0xffff;
273 uint32_t api = (badvaddr >> 22) & 0x3f;
274
[da1bafb]275 uint32_t vsid = sr_get(badvaddr);
276 uint32_t sdr1 = sdr1_get();
[896ad9f]277
[da1bafb]278 // FIXME: compute size of PHT exactly
[896ad9f]279 phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000);
280
281 /* Primary hash (xor) */
282 uint32_t h = 0;
283 uint32_t hash = vsid ^ page;
284 uint32_t base = (hash & 0x3ff) << 3;
285 uint32_t i;
286 bool found = false;
287
[1e241723]288 /* Find colliding PTE in PTEG */
[896ad9f]289 for (i = 0; i < 8; i++) {
[1e241723]290 if ((phte_real[base + i].v)
291 && (phte_real[base + i].vsid == vsid)
[896ad9f]292 && (phte_real[base + i].api == api)
[1e241723]293 && (phte_real[base + i].h == 0)) {
[896ad9f]294 found = true;
295 break;
296 }
[10e0cee]297 }
298
[1e241723]299 if (!found) {
300 /* Find unused PTE in PTEG */
301 for (i = 0; i < 8; i++) {
302 if (!phte_real[base + i].v) {
303 found = true;
304 break;
305 }
306 }
307 }
308
[896ad9f]309 if (!found) {
310 /* Secondary hash (not) */
311 uint32_t base2 = (~hash & 0x3ff) << 3;
312
[1e241723]313 /* Find colliding PTE in PTEG */
[896ad9f]314 for (i = 0; i < 8; i++) {
[1e241723]315 if ((phte_real[base2 + i].v)
316 && (phte_real[base2 + i].vsid == vsid)
[896ad9f]317 && (phte_real[base2 + i].api == api)
[1e241723]318 && (phte_real[base2 + i].h == 1)) {
[896ad9f]319 found = true;
320 base = base2;
321 h = 1;
322 break;
323 }
324 }
325
[1e241723]326 if (!found) {
327 /* Find unused PTE in PTEG */
328 for (i = 0; i < 8; i++) {
329 if (!phte_real[base2 + i].v) {
330 found = true;
331 base = base2;
332 h = 1;
333 break;
334 }
335 }
336 }
337
[896ad9f]338 if (!found) {
339 /* Use secondary hash to avoid collisions
340 with usual PHT refill handler. */
341 i = RANDI(seed_real) % 8;
342 base = base2;
343 h = 1;
344 }
345 }
346
347 phte_real[base + i].v = 1;
348 phte_real[base + i].vsid = vsid;
349 phte_real[base + i].h = h;
350 phte_real[base + i].api = api;
351 phte_real[base + i].rpn = KA2PA(badvaddr) >> 12;
352 phte_real[base + i].r = 0;
353 phte_real[base + i].c = 0;
354 phte_real[base + i].wimg = 0;
355 phte_real[base + i].pp = 2; // FIXME
356
357 return true;
[10e0cee]358}
359
[0867321]360/** Process ITLB/DTLB Miss Exception in Real Mode
361 *
362 *
363 */
[5954241]364void tlb_refill_real(unsigned int n, uint32_t tlbmiss, ptehi_t ptehi,
365 ptelo_t ptelo, istate_t *istate)
[0867321]366{
367 uint32_t badvaddr = tlbmiss & 0xfffffffc;
[da1bafb]368 uint32_t physmem = physmem_top();
[0867321]369
370 if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem)))
371 return; // FIXME
372
373 ptelo.rpn = KA2PA(badvaddr) >> 12;
374 ptelo.wimg = 0;
375 ptelo.pp = 2; // FIXME
376
377 uint32_t index = 0;
378 asm volatile (
[da1bafb]379 "mtspr 981, %[ptehi]\n"
380 "mtspr 982, %[ptelo]\n"
381 "tlbld %[index]\n"
382 "tlbli %[index]\n"
383 : [index] "=r" (index)
384 : [ptehi] "r" (ptehi),
385 [ptelo] "r" (ptelo)
[0867321]386 );
387}
388
[613bc54]389void tlb_arch_init(void)
[a33c990]390{
391 tlb_invalidate_all();
392}
393
394void tlb_invalidate_all(void)
[613bc54]395{
[7b187ef]396 uint32_t index;
[da1bafb]397
[9a68b34d]398 asm volatile (
[da1bafb]399 "li %[index], 0\n"
[7b187ef]400 "sync\n"
401
[e731b0d]402 ".rept 64\n"
[da1bafb]403 " tlbie %[index]\n"
404 " addi %[index], %[index], 0x1000\n"
[e731b0d]405 ".endr\n"
[7b187ef]406
407 "eieio\n"
[a33c990]408 "tlbsync\n"
[7b187ef]409 "sync\n"
[da1bafb]410 : [index] "=r" (index)
[9a68b34d]411 );
[613bc54]412}
413
[a33c990]414void tlb_invalidate_asid(asid_t asid)
[68965ec5]415{
[da1bafb]416 uint32_t sdr1 = sdr1_get();
417
418 // FIXME: compute size of PHT exactly
[2c8a70a]419 phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
420
[da1bafb]421 size_t i;
[2c8a70a]422 for (i = 0; i < 8192; i++) {
[5d67baa]423 if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) &&
424 (phte[i].vsid < ((asid << 4) + 16)))
[2c8a70a]425 phte[i].v = 0;
426 }
[da1bafb]427
[a33c990]428 tlb_invalidate_all();
[68965ec5]429}
430
[98000fb]431void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
[a33c990]432{
[10e0cee]433 // TODO
[a33c990]434 tlb_invalidate_all();
435}
436
[e600ec4]437#define PRINT_BAT(name, ureg, lreg) \
438 asm volatile ( \
[da1bafb]439 "mfspr %[upper], " #ureg "\n" \
440 "mfspr %[lower], " #lreg "\n" \
441 : [upper] "=r" (upper), \
442 [lower] "=r" (lower) \
[e600ec4]443 ); \
[da1bafb]444 \
[e600ec4]445 mask = (upper & 0x1ffc) >> 2; \
446 if (upper & 3) { \
[7f1c620]447 uint32_t tmp = mask; \
[e600ec4]448 length = 128; \
[da1bafb]449 \
[e600ec4]450 while (tmp) { \
451 if ((tmp & 1) == 0) { \
452 printf("ibat[0]: error in mask\n"); \
453 break; \
454 } \
455 length <<= 1; \
456 tmp >>= 1; \
457 } \
458 } else \
459 length = 0; \
[da1bafb]460 \
[5d67baa]461 printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \
462 sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \
463 lower & 0xffff0000, length, mask, \
464 ((upper >> 1) & 1) ? " supervisor" : "", \
465 (upper & 1) ? " user" : "");
[e600ec4]466
467
[613bc54]468void tlb_print(void)
469{
[7f1c620]470 uint32_t sr;
[cf84d72a]471
472 for (sr = 0; sr < 16; sr++) {
[da1bafb]473 uint32_t vsid = sr_get(sr << 28);
474
[896ad9f]475 printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr,
[5d67baa]476 sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,
477 ((vsid >> 30) & 1) ? " supervisor" : "",
478 ((vsid >> 29) & 1) ? " user" : "");
[cf84d72a]479 }
[e600ec4]480
[7f1c620]481 uint32_t upper;
482 uint32_t lower;
483 uint32_t mask;
484 uint32_t length;
[e600ec4]485
486 PRINT_BAT("ibat[0]", 528, 529);
487 PRINT_BAT("ibat[1]", 530, 531);
488 PRINT_BAT("ibat[2]", 532, 533);
489 PRINT_BAT("ibat[3]", 534, 535);
490
491 PRINT_BAT("dbat[0]", 536, 537);
492 PRINT_BAT("dbat[1]", 538, 539);
493 PRINT_BAT("dbat[2]", 540, 541);
494 PRINT_BAT("dbat[3]", 542, 543);
[613bc54]495}
[b45c443]496
[10e0cee]497/** @}
[b45c443]498 */
Note: See TracBrowser for help on using the repository browser.