source: mainline/kernel/arch/ppc32/src/interrupt.c@ adec5b45

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since adec5b45 was eef1b031, checked in by Martin Decky <martin@…>, 14 years ago

ppc32: page hash table should be no longer interpreted as a TLB, it is really closer to the TSB on sparc64
this fixes ticket #344 for ppc32

  • Property mode set to 100644
File size: 4.9 KB
Line 
1/*
2 * Copyright (c) 2006 Martin Decky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ppc32interrupt
30 * @{
31 */
32/** @file
33 */
34
35#include <ddi/irq.h>
36#include <interrupt.h>
37#include <arch/interrupt.h>
38#include <typedefs.h>
39#include <arch.h>
40#include <time/clock.h>
41#include <ipc/sysipc.h>
42#include <arch/drivers/pic.h>
43#include <arch/mm/tlb.h>
44#include <arch/mm/pht.h>
45#include <print.h>
46
47void start_decrementer(void)
48{
49 asm volatile (
50 "mtdec %[dec]\n"
51 :: [dec] "r" (1000)
52 );
53}
54
55void istate_decode(istate_t *istate)
56{
57 printf("r0 =%0#10" PRIx32 "\tr1 =%0#10" PRIx32 "\t"
58 "r2 =%0#10" PRIx32 "\n", istate->r0, istate->sp, istate->r2);
59
60 printf("r3 =%0#10" PRIx32 "\tr4 =%0#10" PRIx32 "\t"
61 "r5 =%0#10" PRIx32 "\n", istate->r3, istate->r4, istate->r5);
62
63 printf("r6 =%0#10" PRIx32 "\tr7 =%0#10" PRIx32 "\t"
64 "r8 =%0#10" PRIx32 "\n", istate->r6, istate->r7, istate->r8);
65
66 printf("r9 =%0#10" PRIx32 "\tr10=%0#10" PRIx32 "\t"
67 "r11=%0#10" PRIx32 "\n", istate->r9, istate->r10, istate->r11);
68
69 printf("r12=%0#10" PRIx32 "\tr13=%0#10" PRIx32 "\t"
70 "r14=%0#10" PRIx32 "\n", istate->r12, istate->r13, istate->r14);
71
72 printf("r15=%0#10" PRIx32 "\tr16=%0#10" PRIx32 "\t"
73 "r17=%0#10" PRIx32 "\n", istate->r15, istate->r16, istate->r17);
74
75 printf("r18=%0#10" PRIx32 "\tr19=%0#10" PRIx32 "\t"
76 "r20=%0#10" PRIx32 "\n", istate->r18, istate->r19, istate->r20);
77
78 printf("r21=%0#10" PRIx32 "\tr22=%0#10" PRIx32 "\t"
79 "r23=%0#10" PRIx32 "\n", istate->r21, istate->r22, istate->r23);
80
81 printf("r24=%0#10" PRIx32 "\tr25=%0#10" PRIx32 "\t"
82 "r26=%0#10" PRIx32 "\n", istate->r24, istate->r25, istate->r26);
83
84 printf("r27=%0#10" PRIx32 "\tr28=%0#10" PRIx32 "\t"
85 "r29=%0#10" PRIx32 "\n", istate->r27, istate->r28, istate->r29);
86
87 printf("r30=%0#10" PRIx32 "\tr31=%0#10" PRIx32 "\n",
88 istate->r30, istate->r31);
89
90 printf("cr =%0#10" PRIx32 "\tpc =%0#10" PRIx32 "\t"
91 "lr =%0#10" PRIx32 "\n", istate->cr, istate->pc, istate->lr);
92
93 printf("ctr=%0#10" PRIx32 "\txer=%0#10" PRIx32 "\t"
94 "dar=%0#10" PRIx32 "\n", istate->ctr, istate->xer, istate->dar);
95
96 printf("srr1=%0#10" PRIx32 "\n", istate->srr1);
97}
98
99/** External interrupts handler
100 *
101 */
102static void exception_external(unsigned int n, istate_t *istate)
103{
104 uint8_t inum;
105
106 while ((inum = pic_get_pending()) != 255) {
107 irq_t *irq = irq_dispatch_and_lock(inum);
108 if (irq) {
109 /*
110 * The IRQ handler was found.
111 */
112
113 if (irq->preack) {
114 /* Acknowledge the interrupt before processing */
115 if (irq->cir)
116 irq->cir(irq->cir_arg, irq->inr);
117 }
118
119 irq->handler(irq);
120
121 if (!irq->preack) {
122 if (irq->cir)
123 irq->cir(irq->cir_arg, irq->inr);
124 }
125
126 irq_spinlock_unlock(&irq->lock, false);
127 } else {
128 /*
129 * Spurious interrupt.
130 */
131#ifdef CONFIG_DEBUG
132 printf("cpu%u: spurious interrupt (inum=%" PRIu8 ")\n",
133 CPU->id, inum);
134#endif
135 }
136 }
137}
138
139static void exception_decrementer(unsigned int n, istate_t *istate)
140{
141 start_decrementer();
142 clock();
143}
144
145/* Initialize basic tables for exception dispatching */
146void interrupt_init(void)
147{
148 exc_register(VECTOR_DATA_STORAGE, "data_storage", true,
149 pht_refill);
150 exc_register(VECTOR_INSTRUCTION_STORAGE, "instruction_storage", true,
151 pht_refill);
152 exc_register(VECTOR_EXTERNAL, "external", true,
153 exception_external);
154 exc_register(VECTOR_DECREMENTER, "timer", true,
155 exception_decrementer);
156 exc_register(VECTOR_ITLB_MISS, "itlb_miss", true,
157 tlb_refill);
158 exc_register(VECTOR_DTLB_MISS_LOAD, "dtlb_miss_load", true,
159 tlb_refill);
160 exc_register(VECTOR_DTLB_MISS_STORE, "dtlb_miss_store", true,
161 tlb_refill);
162}
163
164/** @}
165 */
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