| 1 | /* | 
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| 2 | * Copyright (c) 2006 Martin Decky | 
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| 3 | * All rights reserved. | 
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| 4 | * | 
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| 5 | * Redistribution and use in source and binary forms, with or without | 
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| 6 | * modification, are permitted provided that the following conditions | 
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| 7 | * are met: | 
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| 8 | * | 
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| 9 | * - Redistributions of source code must retain the above copyright | 
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| 10 | *   notice, this list of conditions and the following disclaimer. | 
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| 11 | * - Redistributions in binary form must reproduce the above copyright | 
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| 12 | *   notice, this list of conditions and the following disclaimer in the | 
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| 13 | *   documentation and/or other materials provided with the distribution. | 
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| 14 | * - The name of the author may not be used to endorse or promote products | 
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| 15 | *   derived from this software without specific prior written permission. | 
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| 16 | * | 
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR | 
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | 
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. | 
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | 
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | 
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | 
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | 
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | 
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | 
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | 
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| 27 | */ | 
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| 28 |  | 
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| 29 | /** @addtogroup kernel_ppc32_interrupt | 
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| 30 | * @{ | 
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| 31 | */ | 
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| 32 | /** @file | 
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| 33 | */ | 
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| 34 |  | 
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| 35 | #include <ddi/irq.h> | 
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| 36 | #include <interrupt.h> | 
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| 37 | #include <arch/interrupt.h> | 
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| 38 | #include <arch/istate.h> | 
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| 39 | #include <stdint.h> | 
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| 40 | #include <arch.h> | 
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| 41 | #include <ipc/sysipc.h> | 
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| 42 | #include <arch/drivers/pic.h> | 
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| 43 | #include <arch/mm/tlb.h> | 
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| 44 | #include <arch/mm/pht.h> | 
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| 45 | #include <log.h> | 
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| 46 |  | 
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| 47 | static uint32_t decrementer_value; | 
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| 48 |  | 
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| 49 | void decrementer_start(uint32_t val) | 
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| 50 | { | 
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| 51 | decrementer_value = val; | 
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| 52 | decrementer_restart(); | 
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| 53 | } | 
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| 54 |  | 
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| 55 | void decrementer_restart(void) | 
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| 56 | { | 
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| 57 | asm volatile ( | 
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| 58 | "mtdec %[dec]\n" | 
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| 59 | :: [dec] "r" (decrementer_value) | 
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| 60 | ); | 
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| 61 | } | 
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| 62 |  | 
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| 63 | void istate_decode(istate_t *istate) | 
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| 64 | { | 
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| 65 | log_printf("r0 =%0#10" PRIx32 "\tr1 =%0#10" PRIx32 "\t" | 
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| 66 | "r2 =%0#10" PRIx32 "\n", istate->r0, istate->sp, istate->r2); | 
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| 67 |  | 
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| 68 | log_printf("r3 =%0#10" PRIx32 "\tr4 =%0#10" PRIx32 "\t" | 
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| 69 | "r5 =%0#10" PRIx32 "\n", istate->r3, istate->r4, istate->r5); | 
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| 70 |  | 
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| 71 | log_printf("r6 =%0#10" PRIx32 "\tr7 =%0#10" PRIx32 "\t" | 
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| 72 | "r8 =%0#10" PRIx32 "\n", istate->r6, istate->r7, istate->r8); | 
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| 73 |  | 
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| 74 | log_printf("r9 =%0#10" PRIx32 "\tr10=%0#10" PRIx32 "\t" | 
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| 75 | "r11=%0#10" PRIx32 "\n", istate->r9, istate->r10, istate->r11); | 
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| 76 |  | 
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| 77 | log_printf("r12=%0#10" PRIx32 "\tr13=%0#10" PRIx32 "\t" | 
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| 78 | "r14=%0#10" PRIx32 "\n", istate->r12, istate->r13, istate->r14); | 
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| 79 |  | 
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| 80 | log_printf("r15=%0#10" PRIx32 "\tr16=%0#10" PRIx32 "\t" | 
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| 81 | "r17=%0#10" PRIx32 "\n", istate->r15, istate->r16, istate->r17); | 
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| 82 |  | 
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| 83 | log_printf("r18=%0#10" PRIx32 "\tr19=%0#10" PRIx32 "\t" | 
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| 84 | "r20=%0#10" PRIx32 "\n", istate->r18, istate->r19, istate->r20); | 
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| 85 |  | 
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| 86 | log_printf("r21=%0#10" PRIx32 "\tr22=%0#10" PRIx32 "\t" | 
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| 87 | "r23=%0#10" PRIx32 "\n", istate->r21, istate->r22, istate->r23); | 
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| 88 |  | 
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| 89 | log_printf("r24=%0#10" PRIx32 "\tr25=%0#10" PRIx32 "\t" | 
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| 90 | "r26=%0#10" PRIx32 "\n", istate->r24, istate->r25, istate->r26); | 
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| 91 |  | 
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| 92 | log_printf("r27=%0#10" PRIx32 "\tr28=%0#10" PRIx32 "\t" | 
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| 93 | "r29=%0#10" PRIx32 "\n", istate->r27, istate->r28, istate->r29); | 
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| 94 |  | 
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| 95 | log_printf("r30=%0#10" PRIx32 "\tr31=%0#10" PRIx32 "\n", | 
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| 96 | istate->r30, istate->r31); | 
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| 97 |  | 
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| 98 | log_printf("cr =%0#10" PRIx32 "\tpc =%0#10" PRIx32 "\t" | 
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| 99 | "lr =%0#10" PRIx32 "\n", istate->cr, istate->pc, istate->lr); | 
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| 100 |  | 
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| 101 | log_printf("ctr=%0#10" PRIx32 "\txer=%0#10" PRIx32 "\t" | 
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| 102 | "dar=%0#10" PRIx32 "\n", istate->ctr, istate->xer, istate->dar); | 
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| 103 |  | 
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| 104 | log_printf("srr1=%0#10" PRIx32 "\n", istate->srr1); | 
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| 105 | } | 
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| 106 |  | 
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| 107 | /** External interrupts handler | 
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| 108 | * | 
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| 109 | */ | 
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| 110 | static void exception_external(unsigned int n, istate_t *istate) | 
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| 111 | { | 
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| 112 | uint8_t inum; | 
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| 113 |  | 
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| 114 | while ((inum = pic_get_pending()) != 255) { | 
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| 115 | irq_t *irq = irq_dispatch_and_lock(inum); | 
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| 116 | if (irq) { | 
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| 117 | /* | 
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| 118 | * The IRQ handler was found. | 
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| 119 | */ | 
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| 120 |  | 
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| 121 | if (irq->preack) { | 
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| 122 | /* Acknowledge the interrupt before processing */ | 
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| 123 | if (irq->cir) | 
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| 124 | irq->cir(irq->cir_arg, irq->inr); | 
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| 125 | } | 
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| 126 |  | 
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| 127 | irq->handler(irq); | 
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| 128 |  | 
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| 129 | if (!irq->preack) { | 
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| 130 | if (irq->cir) | 
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| 131 | irq->cir(irq->cir_arg, irq->inr); | 
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| 132 | } | 
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| 133 |  | 
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| 134 | irq_spinlock_unlock(&irq->lock, false); | 
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| 135 | } else { | 
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| 136 | /* | 
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| 137 | * Spurious interrupt. | 
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| 138 | */ | 
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| 139 | #ifdef CONFIG_DEBUG | 
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| 140 | log(LF_ARCH, LVL_DEBUG, "cpu%u: spurious interrupt" | 
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| 141 | " (inum=%" PRIu8 ")", CPU->id, inum); | 
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| 142 | #endif | 
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| 143 | pic_ack_interrupt(NULL, inum); | 
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| 144 | break; | 
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| 145 | } | 
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| 146 | } | 
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| 147 | } | 
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| 148 |  | 
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| 149 | static void exception_fp_unavailable(unsigned int n, istate_t *istate) | 
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| 150 | { | 
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| 151 | #ifdef CONFIG_FPU_LAZY | 
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| 152 | scheduler_fpu_lazy_request(); | 
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| 153 | /* | 
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| 154 | * Propagate MSR_FP from MSR back to istate's SRR1, which will become | 
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| 155 | * the next MSR. | 
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| 156 | */ | 
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| 157 | istate->srr1 |= msr_read() & MSR_FP; | 
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| 158 | #else | 
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| 159 | fault_if_from_uspace(istate, "FPU fault."); | 
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| 160 | panic_badtrap(istate, n, "FPU fault."); | 
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| 161 | #endif | 
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| 162 | } | 
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| 163 |  | 
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| 164 | static void exception_decrementer(unsigned int n, istate_t *istate) | 
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| 165 | { | 
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| 166 | decrementer_restart(); | 
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| 167 | clock(); | 
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| 168 | } | 
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| 169 |  | 
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| 170 | /* Initialize basic tables for exception dispatching */ | 
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| 171 | void interrupt_init(void) | 
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| 172 | { | 
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| 173 | exc_register(VECTOR_DATA_STORAGE, "data_storage", true, | 
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| 174 | pht_refill); | 
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| 175 | exc_register(VECTOR_INSTRUCTION_STORAGE, "instruction_storage", true, | 
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| 176 | pht_refill); | 
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| 177 | exc_register(VECTOR_EXTERNAL, "external", true, | 
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| 178 | exception_external); | 
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| 179 | exc_register(VECTOR_FP_UNAVAILABLE, "fp_unavailable", true, | 
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| 180 | exception_fp_unavailable); | 
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| 181 | exc_register(VECTOR_DECREMENTER, "timer", true, | 
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| 182 | exception_decrementer); | 
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| 183 | exc_register(VECTOR_ITLB_MISS, "itlb_miss", true, | 
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| 184 | tlb_refill); | 
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| 185 | exc_register(VECTOR_DTLB_MISS_LOAD, "dtlb_miss_load", true, | 
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| 186 | tlb_refill); | 
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| 187 | exc_register(VECTOR_DTLB_MISS_STORE, "dtlb_miss_store", true, | 
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| 188 | tlb_refill); | 
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| 189 | } | 
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| 190 |  | 
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| 191 | /** @} | 
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| 192 | */ | 
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