source: mainline/kernel/arch/ppc32/src/interrupt.c@ 566da7f8

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 566da7f8 was b2fa1204, checked in by Martin Sucha <sucha14@…>, 12 years ago

Cherrypick usage of kernel logger

  • Property mode set to 100644
File size: 5.0 KB
Line 
1/*
2 * Copyright (c) 2006 Martin Decky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ppc32interrupt
30 * @{
31 */
32/** @file
33 */
34
35#include <ddi/irq.h>
36#include <interrupt.h>
37#include <arch/interrupt.h>
38#include <typedefs.h>
39#include <arch.h>
40#include <time/clock.h>
41#include <ipc/sysipc.h>
42#include <arch/drivers/pic.h>
43#include <arch/mm/tlb.h>
44#include <arch/mm/pht.h>
45#include <print.h>
46#include <log.h>
47
48void start_decrementer(void)
49{
50 asm volatile (
51 "mtdec %[dec]\n"
52 :: [dec] "r" (1000)
53 );
54}
55
56void istate_decode(istate_t *istate)
57{
58 log_printf("r0 =%0#10" PRIx32 "\tr1 =%0#10" PRIx32 "\t"
59 "r2 =%0#10" PRIx32 "\n", istate->r0, istate->sp, istate->r2);
60
61 log_printf("r3 =%0#10" PRIx32 "\tr4 =%0#10" PRIx32 "\t"
62 "r5 =%0#10" PRIx32 "\n", istate->r3, istate->r4, istate->r5);
63
64 log_printf("r6 =%0#10" PRIx32 "\tr7 =%0#10" PRIx32 "\t"
65 "r8 =%0#10" PRIx32 "\n", istate->r6, istate->r7, istate->r8);
66
67 log_printf("r9 =%0#10" PRIx32 "\tr10=%0#10" PRIx32 "\t"
68 "r11=%0#10" PRIx32 "\n", istate->r9, istate->r10, istate->r11);
69
70 log_printf("r12=%0#10" PRIx32 "\tr13=%0#10" PRIx32 "\t"
71 "r14=%0#10" PRIx32 "\n", istate->r12, istate->r13, istate->r14);
72
73 log_printf("r15=%0#10" PRIx32 "\tr16=%0#10" PRIx32 "\t"
74 "r17=%0#10" PRIx32 "\n", istate->r15, istate->r16, istate->r17);
75
76 log_printf("r18=%0#10" PRIx32 "\tr19=%0#10" PRIx32 "\t"
77 "r20=%0#10" PRIx32 "\n", istate->r18, istate->r19, istate->r20);
78
79 log_printf("r21=%0#10" PRIx32 "\tr22=%0#10" PRIx32 "\t"
80 "r23=%0#10" PRIx32 "\n", istate->r21, istate->r22, istate->r23);
81
82 log_printf("r24=%0#10" PRIx32 "\tr25=%0#10" PRIx32 "\t"
83 "r26=%0#10" PRIx32 "\n", istate->r24, istate->r25, istate->r26);
84
85 log_printf("r27=%0#10" PRIx32 "\tr28=%0#10" PRIx32 "\t"
86 "r29=%0#10" PRIx32 "\n", istate->r27, istate->r28, istate->r29);
87
88 log_printf("r30=%0#10" PRIx32 "\tr31=%0#10" PRIx32 "\n",
89 istate->r30, istate->r31);
90
91 log_printf("cr =%0#10" PRIx32 "\tpc =%0#10" PRIx32 "\t"
92 "lr =%0#10" PRIx32 "\n", istate->cr, istate->pc, istate->lr);
93
94 log_printf("ctr=%0#10" PRIx32 "\txer=%0#10" PRIx32 "\t"
95 "dar=%0#10" PRIx32 "\n", istate->ctr, istate->xer, istate->dar);
96
97 log_printf("srr1=%0#10" PRIx32 "\n", istate->srr1);
98}
99
100/** External interrupts handler
101 *
102 */
103static void exception_external(unsigned int n, istate_t *istate)
104{
105 uint8_t inum;
106
107 while ((inum = pic_get_pending()) != 255) {
108 irq_t *irq = irq_dispatch_and_lock(inum);
109 if (irq) {
110 /*
111 * The IRQ handler was found.
112 */
113
114 if (irq->preack) {
115 /* Acknowledge the interrupt before processing */
116 if (irq->cir)
117 irq->cir(irq->cir_arg, irq->inr);
118 }
119
120 irq->handler(irq);
121
122 if (!irq->preack) {
123 if (irq->cir)
124 irq->cir(irq->cir_arg, irq->inr);
125 }
126
127 irq_spinlock_unlock(&irq->lock, false);
128 } else {
129 /*
130 * Spurious interrupt.
131 */
132#ifdef CONFIG_DEBUG
133 log(LF_ARCH, LVL_DEBUG, "cpu%u: spurious interrupt"
134 " (inum=%" PRIu8 ")", CPU->id, inum);
135#endif
136 }
137 }
138}
139
140static void exception_decrementer(unsigned int n, istate_t *istate)
141{
142 start_decrementer();
143 clock();
144}
145
146/* Initialize basic tables for exception dispatching */
147void interrupt_init(void)
148{
149 exc_register(VECTOR_DATA_STORAGE, "data_storage", true,
150 pht_refill);
151 exc_register(VECTOR_INSTRUCTION_STORAGE, "instruction_storage", true,
152 pht_refill);
153 exc_register(VECTOR_EXTERNAL, "external", true,
154 exception_external);
155 exc_register(VECTOR_DECREMENTER, "timer", true,
156 exception_decrementer);
157 exc_register(VECTOR_ITLB_MISS, "itlb_miss", true,
158 tlb_refill);
159 exc_register(VECTOR_DTLB_MISS_LOAD, "dtlb_miss_load", true,
160 tlb_refill);
161 exc_register(VECTOR_DTLB_MISS_STORE, "dtlb_miss_store", true,
162 tlb_refill);
163}
164
165/** @}
166 */
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