source: mainline/kernel/arch/ppc32/src/interrupt.c@ 3061bc1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3061bc1 was 83dab11, checked in by Jiri Svoboda <jiri@…>, 8 years ago

Replace usage of typedefs.h with includes of more specific, standard headers, where applicable.

  • Property mode set to 100644
File size: 5.6 KB
Line 
1/*
2 * Copyright (c) 2006 Martin Decky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ppc32interrupt
30 * @{
31 */
32/** @file
33 */
34
35#include <ddi/irq.h>
36#include <interrupt.h>
37#include <arch/interrupt.h>
38#include <arch/istate.h>
39#include <stdint.h>
40#include <arch.h>
41#include <ipc/sysipc.h>
42#include <arch/drivers/pic.h>
43#include <arch/mm/tlb.h>
44#include <arch/mm/pht.h>
45#include <print.h>
46#include <log.h>
47
48static uint32_t decrementer_value;
49
50void decrementer_start(uint32_t val)
51{
52 decrementer_value = val;
53 decrementer_restart();
54}
55
56void decrementer_restart(void)
57{
58 asm volatile (
59 "mtdec %[dec]\n"
60 :: [dec] "r" (decrementer_value)
61 );
62}
63
64void istate_decode(istate_t *istate)
65{
66 log_printf("r0 =%0#10" PRIx32 "\tr1 =%0#10" PRIx32 "\t"
67 "r2 =%0#10" PRIx32 "\n", istate->r0, istate->sp, istate->r2);
68
69 log_printf("r3 =%0#10" PRIx32 "\tr4 =%0#10" PRIx32 "\t"
70 "r5 =%0#10" PRIx32 "\n", istate->r3, istate->r4, istate->r5);
71
72 log_printf("r6 =%0#10" PRIx32 "\tr7 =%0#10" PRIx32 "\t"
73 "r8 =%0#10" PRIx32 "\n", istate->r6, istate->r7, istate->r8);
74
75 log_printf("r9 =%0#10" PRIx32 "\tr10=%0#10" PRIx32 "\t"
76 "r11=%0#10" PRIx32 "\n", istate->r9, istate->r10, istate->r11);
77
78 log_printf("r12=%0#10" PRIx32 "\tr13=%0#10" PRIx32 "\t"
79 "r14=%0#10" PRIx32 "\n", istate->r12, istate->r13, istate->r14);
80
81 log_printf("r15=%0#10" PRIx32 "\tr16=%0#10" PRIx32 "\t"
82 "r17=%0#10" PRIx32 "\n", istate->r15, istate->r16, istate->r17);
83
84 log_printf("r18=%0#10" PRIx32 "\tr19=%0#10" PRIx32 "\t"
85 "r20=%0#10" PRIx32 "\n", istate->r18, istate->r19, istate->r20);
86
87 log_printf("r21=%0#10" PRIx32 "\tr22=%0#10" PRIx32 "\t"
88 "r23=%0#10" PRIx32 "\n", istate->r21, istate->r22, istate->r23);
89
90 log_printf("r24=%0#10" PRIx32 "\tr25=%0#10" PRIx32 "\t"
91 "r26=%0#10" PRIx32 "\n", istate->r24, istate->r25, istate->r26);
92
93 log_printf("r27=%0#10" PRIx32 "\tr28=%0#10" PRIx32 "\t"
94 "r29=%0#10" PRIx32 "\n", istate->r27, istate->r28, istate->r29);
95
96 log_printf("r30=%0#10" PRIx32 "\tr31=%0#10" PRIx32 "\n",
97 istate->r30, istate->r31);
98
99 log_printf("cr =%0#10" PRIx32 "\tpc =%0#10" PRIx32 "\t"
100 "lr =%0#10" PRIx32 "\n", istate->cr, istate->pc, istate->lr);
101
102 log_printf("ctr=%0#10" PRIx32 "\txer=%0#10" PRIx32 "\t"
103 "dar=%0#10" PRIx32 "\n", istate->ctr, istate->xer, istate->dar);
104
105 log_printf("srr1=%0#10" PRIx32 "\n", istate->srr1);
106}
107
108/** External interrupts handler
109 *
110 */
111static void exception_external(unsigned int n, istate_t *istate)
112{
113 uint8_t inum;
114
115 while ((inum = pic_get_pending()) != 255) {
116 irq_t *irq = irq_dispatch_and_lock(inum);
117 if (irq) {
118 /*
119 * The IRQ handler was found.
120 */
121
122 if (irq->preack) {
123 /* Acknowledge the interrupt before processing */
124 if (irq->cir)
125 irq->cir(irq->cir_arg, irq->inr);
126 }
127
128 irq->handler(irq);
129
130 if (!irq->preack) {
131 if (irq->cir)
132 irq->cir(irq->cir_arg, irq->inr);
133 }
134
135 irq_spinlock_unlock(&irq->lock, false);
136 } else {
137 /*
138 * Spurious interrupt.
139 */
140#ifdef CONFIG_DEBUG
141 log(LF_ARCH, LVL_DEBUG, "cpu%u: spurious interrupt"
142 " (inum=%" PRIu8 ")", CPU->id, inum);
143#endif
144 }
145 }
146}
147
148static void exception_fp_unavailable(unsigned int n, istate_t *istate)
149{
150#ifdef CONFIG_FPU_LAZY
151 scheduler_fpu_lazy_request();
152 /*
153 * Propagate MSR_FP from MSR back to istate's SRR1, which will become
154 * the next MSR.
155 */
156 istate->srr1 |= msr_read() & MSR_FP;
157#else
158 fault_if_from_uspace(istate, "FPU fault.");
159 panic_badtrap(istate, n, "FPU fault.");
160#endif
161}
162
163static void exception_decrementer(unsigned int n, istate_t *istate)
164{
165 decrementer_restart();
166 clock();
167}
168
169/* Initialize basic tables for exception dispatching */
170void interrupt_init(void)
171{
172 exc_register(VECTOR_DATA_STORAGE, "data_storage", true,
173 pht_refill);
174 exc_register(VECTOR_INSTRUCTION_STORAGE, "instruction_storage", true,
175 pht_refill);
176 exc_register(VECTOR_EXTERNAL, "external", true,
177 exception_external);
178 exc_register(VECTOR_FP_UNAVAILABLE, "fp_unavailable", true,
179 exception_fp_unavailable);
180 exc_register(VECTOR_DECREMENTER, "timer", true,
181 exception_decrementer);
182 exc_register(VECTOR_ITLB_MISS, "itlb_miss", true,
183 tlb_refill);
184 exc_register(VECTOR_DTLB_MISS_LOAD, "dtlb_miss_load", true,
185 tlb_refill);
186 exc_register(VECTOR_DTLB_MISS_STORE, "dtlb_miss_store", true,
187 tlb_refill);
188}
189
190/** @}
191 */
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