source: mainline/kernel/arch/ppc32/src/interrupt.c@ df7f5cea

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since df7f5cea was df7f5cea, checked in by Jakub Jermar <jakub@…>, 11 years ago

Experimental support for hard-floats on ppc32.

  • By default disabled.
  • Property mode set to 100644
File size: 5.6 KB
RevLine 
[3debedec]1/*
[df4ed85]2 * Copyright (c) 2006 Martin Decky
[3debedec]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[10e0cee]29/** @addtogroup ppc32interrupt
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[f5e39a32]35#include <ddi/irq.h>
[91d5ad6]36#include <interrupt.h>
37#include <arch/interrupt.h>
[6dbe7f68]38#include <arch/istate.h>
[d99c1d2]39#include <typedefs.h>
[91d5ad6]40#include <arch.h>
[953b0f33]41#include <ipc/sysipc.h>
[982f0fe]42#include <arch/drivers/pic.h>
[10e0cee]43#include <arch/mm/tlb.h>
[eef1b031]44#include <arch/mm/pht.h>
[f5e39a32]45#include <print.h>
[b2fa1204]46#include <log.h>
[8965838e]47
[0c91cff]48static uint32_t decrementer_value;
49
50void decrementer_start(uint32_t val)
51{
52 decrementer_value = val;
53 decrementer_restart();
54}
55
56void decrementer_restart(void)
[8965838e]57{
58 asm volatile (
[ffe276f]59 "mtdec %[dec]\n"
[0c91cff]60 :: [dec] "r" (decrementer_value)
[8965838e]61 );
62}
63
[22a28a69]64void istate_decode(istate_t *istate)
[5b8016d]65{
[b2fa1204]66 log_printf("r0 =%0#10" PRIx32 "\tr1 =%0#10" PRIx32 "\t"
[682cfceb]67 "r2 =%0#10" PRIx32 "\n", istate->r0, istate->sp, istate->r2);
[7e752b2]68
[b2fa1204]69 log_printf("r3 =%0#10" PRIx32 "\tr4 =%0#10" PRIx32 "\t"
[682cfceb]70 "r5 =%0#10" PRIx32 "\n", istate->r3, istate->r4, istate->r5);
[7e752b2]71
[b2fa1204]72 log_printf("r6 =%0#10" PRIx32 "\tr7 =%0#10" PRIx32 "\t"
[682cfceb]73 "r8 =%0#10" PRIx32 "\n", istate->r6, istate->r7, istate->r8);
[7e752b2]74
[b2fa1204]75 log_printf("r9 =%0#10" PRIx32 "\tr10=%0#10" PRIx32 "\t"
[682cfceb]76 "r11=%0#10" PRIx32 "\n", istate->r9, istate->r10, istate->r11);
[7e752b2]77
[b2fa1204]78 log_printf("r12=%0#10" PRIx32 "\tr13=%0#10" PRIx32 "\t"
[682cfceb]79 "r14=%0#10" PRIx32 "\n", istate->r12, istate->r13, istate->r14);
[7e752b2]80
[b2fa1204]81 log_printf("r15=%0#10" PRIx32 "\tr16=%0#10" PRIx32 "\t"
[682cfceb]82 "r17=%0#10" PRIx32 "\n", istate->r15, istate->r16, istate->r17);
[7e752b2]83
[b2fa1204]84 log_printf("r18=%0#10" PRIx32 "\tr19=%0#10" PRIx32 "\t"
[682cfceb]85 "r20=%0#10" PRIx32 "\n", istate->r18, istate->r19, istate->r20);
[7e752b2]86
[b2fa1204]87 log_printf("r21=%0#10" PRIx32 "\tr22=%0#10" PRIx32 "\t"
[682cfceb]88 "r23=%0#10" PRIx32 "\n", istate->r21, istate->r22, istate->r23);
[7e752b2]89
[b2fa1204]90 log_printf("r24=%0#10" PRIx32 "\tr25=%0#10" PRIx32 "\t"
[682cfceb]91 "r26=%0#10" PRIx32 "\n", istate->r24, istate->r25, istate->r26);
[7e752b2]92
[b2fa1204]93 log_printf("r27=%0#10" PRIx32 "\tr28=%0#10" PRIx32 "\t"
[682cfceb]94 "r29=%0#10" PRIx32 "\n", istate->r27, istate->r28, istate->r29);
[7e752b2]95
[b2fa1204]96 log_printf("r30=%0#10" PRIx32 "\tr31=%0#10" PRIx32 "\n",
[7e752b2]97 istate->r30, istate->r31);
98
[b2fa1204]99 log_printf("cr =%0#10" PRIx32 "\tpc =%0#10" PRIx32 "\t"
[682cfceb]100 "lr =%0#10" PRIx32 "\n", istate->cr, istate->pc, istate->lr);
[7e752b2]101
[b2fa1204]102 log_printf("ctr=%0#10" PRIx32 "\txer=%0#10" PRIx32 "\t"
[682cfceb]103 "dar=%0#10" PRIx32 "\n", istate->ctr, istate->xer, istate->dar);
[7e752b2]104
[b2fa1204]105 log_printf("srr1=%0#10" PRIx32 "\n", istate->srr1);
[5b8016d]106}
107
[ffe276f]108/** External interrupts handler
109 *
110 */
[5954241]111static void exception_external(unsigned int n, istate_t *istate)
[c782434]112{
[ffe276f]113 uint8_t inum;
[df7f5cea]114
[ffe276f]115 while ((inum = pic_get_pending()) != 255) {
[f5e39a32]116 irq_t *irq = irq_dispatch_and_lock(inum);
117 if (irq) {
118 /*
119 * The IRQ handler was found.
120 */
[7bcfbbc]121
122 if (irq->preack) {
123 /* Acknowledge the interrupt before processing */
[c2417bc]124 if (irq->cir)
125 irq->cir(irq->cir_arg, irq->inr);
[7bcfbbc]126 }
127
[6cd9aa6]128 irq->handler(irq);
[c2417bc]129
130 if (!irq->preack) {
131 if (irq->cir)
132 irq->cir(irq->cir_arg, irq->inr);
133 }
134
[ffe276f]135 irq_spinlock_unlock(&irq->lock, false);
[f5e39a32]136 } else {
137 /*
138 * Spurious interrupt.
139 */
140#ifdef CONFIG_DEBUG
[b2fa1204]141 log(LF_ARCH, LVL_DEBUG, "cpu%u: spurious interrupt"
142 " (inum=%" PRIu8 ")", CPU->id, inum);
[f5e39a32]143#endif
144 }
[c782434]145 }
146}
147
[df7f5cea]148static void exception_fp_unavailable(unsigned int n, istate_t *istate)
149{
150#ifdef CONFIG_FPU_LAZY
151 scheduler_fpu_lazy_request();
152 /*
153 * Propagate MSR_FP from MSR back to istate's SRR1, which will become
154 * the next MSR.
155 */
156 istate->srr1 |= msr_read() & MSR_FP;
157#else
158 fault_if_from_uspace(istate, "FPU fault.");
159 panic_badtrap(istate, n, "FPU fault.");
160#endif
161}
162
[5954241]163static void exception_decrementer(unsigned int n, istate_t *istate)
[91d5ad6]164{
[0c91cff]165 decrementer_restart();
[2425349]166 clock();
[91d5ad6]167}
[3debedec]168
[91d5ad6]169/* Initialize basic tables for exception dispatching */
170void interrupt_init(void)
171{
[b3b7e14a]172 exc_register(VECTOR_DATA_STORAGE, "data_storage", true,
173 pht_refill);
174 exc_register(VECTOR_INSTRUCTION_STORAGE, "instruction_storage", true,
175 pht_refill);
176 exc_register(VECTOR_EXTERNAL, "external", true,
177 exception_external);
[df7f5cea]178 exc_register(VECTOR_FP_UNAVAILABLE, "fp_unavailable", true,
179 exception_fp_unavailable);
[b3b7e14a]180 exc_register(VECTOR_DECREMENTER, "timer", true,
181 exception_decrementer);
[6c3106f]182 exc_register(VECTOR_ITLB_MISS, "itlb_miss", true,
183 tlb_refill);
184 exc_register(VECTOR_DTLB_MISS_LOAD, "dtlb_miss_load", true,
185 tlb_refill);
186 exc_register(VECTOR_DTLB_MISS_STORE, "dtlb_miss_store", true,
187 tlb_refill);
[91d5ad6]188}
[953b0f33]189
[10e0cee]190/** @}
[b45c443]191 */
Note: See TracBrowser for help on using the repository browser.