[3debedec] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2006 Martin Decky
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[3debedec] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[10e0cee] | 29 | /** @addtogroup ppc32interrupt
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[f5e39a32] | 35 | #include <ddi/irq.h>
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[91d5ad6] | 36 | #include <interrupt.h>
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| 37 | #include <arch/interrupt.h>
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[6dbe7f68] | 38 | #include <arch/istate.h>
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[d99c1d2] | 39 | #include <typedefs.h>
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[91d5ad6] | 40 | #include <arch.h>
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[953b0f33] | 41 | #include <ipc/sysipc.h>
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[982f0fe] | 42 | #include <arch/drivers/pic.h>
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[10e0cee] | 43 | #include <arch/mm/tlb.h>
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[eef1b031] | 44 | #include <arch/mm/pht.h>
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[f5e39a32] | 45 | #include <print.h>
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[b2fa1204] | 46 | #include <log.h>
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[8965838e] | 47 |
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[0c91cff] | 48 | static uint32_t decrementer_value;
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| 49 |
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| 50 | void decrementer_start(uint32_t val)
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| 51 | {
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| 52 | decrementer_value = val;
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| 53 | decrementer_restart();
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| 54 | }
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| 55 |
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| 56 | void decrementer_restart(void)
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[8965838e] | 57 | {
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| 58 | asm volatile (
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[ffe276f] | 59 | "mtdec %[dec]\n"
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[0c91cff] | 60 | :: [dec] "r" (decrementer_value)
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[8965838e] | 61 | );
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| 62 | }
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| 63 |
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[22a28a69] | 64 | void istate_decode(istate_t *istate)
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[5b8016d] | 65 | {
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[b2fa1204] | 66 | log_printf("r0 =%0#10" PRIx32 "\tr1 =%0#10" PRIx32 "\t"
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[682cfceb] | 67 | "r2 =%0#10" PRIx32 "\n", istate->r0, istate->sp, istate->r2);
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[7e752b2] | 68 |
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[b2fa1204] | 69 | log_printf("r3 =%0#10" PRIx32 "\tr4 =%0#10" PRIx32 "\t"
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[682cfceb] | 70 | "r5 =%0#10" PRIx32 "\n", istate->r3, istate->r4, istate->r5);
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[7e752b2] | 71 |
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[b2fa1204] | 72 | log_printf("r6 =%0#10" PRIx32 "\tr7 =%0#10" PRIx32 "\t"
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[682cfceb] | 73 | "r8 =%0#10" PRIx32 "\n", istate->r6, istate->r7, istate->r8);
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[7e752b2] | 74 |
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[b2fa1204] | 75 | log_printf("r9 =%0#10" PRIx32 "\tr10=%0#10" PRIx32 "\t"
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[682cfceb] | 76 | "r11=%0#10" PRIx32 "\n", istate->r9, istate->r10, istate->r11);
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[7e752b2] | 77 |
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[b2fa1204] | 78 | log_printf("r12=%0#10" PRIx32 "\tr13=%0#10" PRIx32 "\t"
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[682cfceb] | 79 | "r14=%0#10" PRIx32 "\n", istate->r12, istate->r13, istate->r14);
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[7e752b2] | 80 |
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[b2fa1204] | 81 | log_printf("r15=%0#10" PRIx32 "\tr16=%0#10" PRIx32 "\t"
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[682cfceb] | 82 | "r17=%0#10" PRIx32 "\n", istate->r15, istate->r16, istate->r17);
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[7e752b2] | 83 |
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[b2fa1204] | 84 | log_printf("r18=%0#10" PRIx32 "\tr19=%0#10" PRIx32 "\t"
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[682cfceb] | 85 | "r20=%0#10" PRIx32 "\n", istate->r18, istate->r19, istate->r20);
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[7e752b2] | 86 |
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[b2fa1204] | 87 | log_printf("r21=%0#10" PRIx32 "\tr22=%0#10" PRIx32 "\t"
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[682cfceb] | 88 | "r23=%0#10" PRIx32 "\n", istate->r21, istate->r22, istate->r23);
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[7e752b2] | 89 |
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[b2fa1204] | 90 | log_printf("r24=%0#10" PRIx32 "\tr25=%0#10" PRIx32 "\t"
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[682cfceb] | 91 | "r26=%0#10" PRIx32 "\n", istate->r24, istate->r25, istate->r26);
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[7e752b2] | 92 |
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[b2fa1204] | 93 | log_printf("r27=%0#10" PRIx32 "\tr28=%0#10" PRIx32 "\t"
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[682cfceb] | 94 | "r29=%0#10" PRIx32 "\n", istate->r27, istate->r28, istate->r29);
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[7e752b2] | 95 |
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[b2fa1204] | 96 | log_printf("r30=%0#10" PRIx32 "\tr31=%0#10" PRIx32 "\n",
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[7e752b2] | 97 | istate->r30, istate->r31);
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| 98 |
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[b2fa1204] | 99 | log_printf("cr =%0#10" PRIx32 "\tpc =%0#10" PRIx32 "\t"
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[682cfceb] | 100 | "lr =%0#10" PRIx32 "\n", istate->cr, istate->pc, istate->lr);
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[7e752b2] | 101 |
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[b2fa1204] | 102 | log_printf("ctr=%0#10" PRIx32 "\txer=%0#10" PRIx32 "\t"
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[682cfceb] | 103 | "dar=%0#10" PRIx32 "\n", istate->ctr, istate->xer, istate->dar);
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[7e752b2] | 104 |
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[b2fa1204] | 105 | log_printf("srr1=%0#10" PRIx32 "\n", istate->srr1);
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[5b8016d] | 106 | }
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| 107 |
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[ffe276f] | 108 | /** External interrupts handler
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| 109 | *
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| 110 | */
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[5954241] | 111 | static void exception_external(unsigned int n, istate_t *istate)
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[c782434] | 112 | {
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[ffe276f] | 113 | uint8_t inum;
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[df7f5cea] | 114 |
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[ffe276f] | 115 | while ((inum = pic_get_pending()) != 255) {
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[f5e39a32] | 116 | irq_t *irq = irq_dispatch_and_lock(inum);
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| 117 | if (irq) {
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| 118 | /*
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| 119 | * The IRQ handler was found.
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| 120 | */
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[7bcfbbc] | 121 |
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| 122 | if (irq->preack) {
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| 123 | /* Acknowledge the interrupt before processing */
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[c2417bc] | 124 | if (irq->cir)
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| 125 | irq->cir(irq->cir_arg, irq->inr);
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[7bcfbbc] | 126 | }
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| 127 |
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[6cd9aa6] | 128 | irq->handler(irq);
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[c2417bc] | 129 |
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| 130 | if (!irq->preack) {
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| 131 | if (irq->cir)
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| 132 | irq->cir(irq->cir_arg, irq->inr);
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| 133 | }
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| 134 |
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[ffe276f] | 135 | irq_spinlock_unlock(&irq->lock, false);
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[f5e39a32] | 136 | } else {
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| 137 | /*
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| 138 | * Spurious interrupt.
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| 139 | */
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| 140 | #ifdef CONFIG_DEBUG
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[b2fa1204] | 141 | log(LF_ARCH, LVL_DEBUG, "cpu%u: spurious interrupt"
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| 142 | " (inum=%" PRIu8 ")", CPU->id, inum);
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[f5e39a32] | 143 | #endif
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| 144 | }
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[c782434] | 145 | }
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| 146 | }
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| 147 |
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[df7f5cea] | 148 | static void exception_fp_unavailable(unsigned int n, istate_t *istate)
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| 149 | {
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| 150 | #ifdef CONFIG_FPU_LAZY
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| 151 | scheduler_fpu_lazy_request();
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| 152 | /*
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| 153 | * Propagate MSR_FP from MSR back to istate's SRR1, which will become
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| 154 | * the next MSR.
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| 155 | */
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| 156 | istate->srr1 |= msr_read() & MSR_FP;
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| 157 | #else
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| 158 | fault_if_from_uspace(istate, "FPU fault.");
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| 159 | panic_badtrap(istate, n, "FPU fault.");
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| 160 | #endif
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| 161 | }
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| 162 |
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[5954241] | 163 | static void exception_decrementer(unsigned int n, istate_t *istate)
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[91d5ad6] | 164 | {
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[0c91cff] | 165 | decrementer_restart();
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[2425349] | 166 | clock();
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[91d5ad6] | 167 | }
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[3debedec] | 168 |
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[91d5ad6] | 169 | /* Initialize basic tables for exception dispatching */
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| 170 | void interrupt_init(void)
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| 171 | {
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[b3b7e14a] | 172 | exc_register(VECTOR_DATA_STORAGE, "data_storage", true,
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| 173 | pht_refill);
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| 174 | exc_register(VECTOR_INSTRUCTION_STORAGE, "instruction_storage", true,
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| 175 | pht_refill);
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| 176 | exc_register(VECTOR_EXTERNAL, "external", true,
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| 177 | exception_external);
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[df7f5cea] | 178 | exc_register(VECTOR_FP_UNAVAILABLE, "fp_unavailable", true,
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| 179 | exception_fp_unavailable);
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[b3b7e14a] | 180 | exc_register(VECTOR_DECREMENTER, "timer", true,
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| 181 | exception_decrementer);
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[6c3106f] | 182 | exc_register(VECTOR_ITLB_MISS, "itlb_miss", true,
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| 183 | tlb_refill);
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| 184 | exc_register(VECTOR_DTLB_MISS_LOAD, "dtlb_miss_load", true,
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| 185 | tlb_refill);
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| 186 | exc_register(VECTOR_DTLB_MISS_STORE, "dtlb_miss_store", true,
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| 187 | tlb_refill);
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[91d5ad6] | 188 | }
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[953b0f33] | 189 |
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[10e0cee] | 190 | /** @}
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[b45c443] | 191 | */
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