source: mainline/kernel/arch/ppc32/src/interrupt.c@ 682cfceb

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 682cfceb was 682cfceb, checked in by Jakub Jermar <jakub@…>, 14 years ago

Fix formatting of ppc32 istate_decode().

  • Property mode set to 100644
File size: 4.7 KB
RevLine 
[3debedec]1/*
[df4ed85]2 * Copyright (c) 2006 Martin Decky
[3debedec]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[10e0cee]29/** @addtogroup ppc32interrupt
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[f5e39a32]35#include <ddi/irq.h>
[91d5ad6]36#include <interrupt.h>
37#include <arch/interrupt.h>
[d99c1d2]38#include <typedefs.h>
[91d5ad6]39#include <arch.h>
40#include <time/clock.h>
[953b0f33]41#include <ipc/sysipc.h>
[982f0fe]42#include <arch/drivers/pic.h>
[10e0cee]43#include <arch/mm/tlb.h>
[f5e39a32]44#include <print.h>
[8965838e]45
46void start_decrementer(void)
47{
48 asm volatile (
[ffe276f]49 "mtdec %[dec]\n"
50 :: [dec] "r" (1000)
[8965838e]51 );
52}
53
[22a28a69]54void istate_decode(istate_t *istate)
[5b8016d]55{
[682cfceb]56 printf("r0 =%0#10" PRIx32 "\tr1 =%0#10" PRIx32 "\t"
57 "r2 =%0#10" PRIx32 "\n", istate->r0, istate->sp, istate->r2);
[7e752b2]58
[682cfceb]59 printf("r3 =%0#10" PRIx32 "\tr4 =%0#10" PRIx32 "\t"
60 "r5 =%0#10" PRIx32 "\n", istate->r3, istate->r4, istate->r5);
[7e752b2]61
[682cfceb]62 printf("r6 =%0#10" PRIx32 "\tr7 =%0#10" PRIx32 "\t"
63 "r8 =%0#10" PRIx32 "\n", istate->r6, istate->r7, istate->r8);
[7e752b2]64
[682cfceb]65 printf("r9 =%0#10" PRIx32 "\tr10=%0#10" PRIx32 "\t"
66 "r11=%0#10" PRIx32 "\n", istate->r9, istate->r10, istate->r11);
[7e752b2]67
[682cfceb]68 printf("r12=%0#10" PRIx32 "\tr13=%0#10" PRIx32 "\t"
69 "r14=%0#10" PRIx32 "\n", istate->r12, istate->r13, istate->r14);
[7e752b2]70
[682cfceb]71 printf("r15=%0#10" PRIx32 "\tr16=%0#10" PRIx32 "\t"
72 "r17=%0#10" PRIx32 "\n", istate->r15, istate->r16, istate->r17);
[7e752b2]73
[682cfceb]74 printf("r18=%0#10" PRIx32 "\tr19=%0#10" PRIx32 "\t"
75 "r20=%0#10" PRIx32 "\n", istate->r18, istate->r19, istate->r20);
[7e752b2]76
[682cfceb]77 printf("r21=%0#10" PRIx32 "\tr22=%0#10" PRIx32 "\t"
78 "r23=%0#10" PRIx32 "\n", istate->r21, istate->r22, istate->r23);
[7e752b2]79
[682cfceb]80 printf("r24=%0#10" PRIx32 "\tr25=%0#10" PRIx32 "\t"
81 "r26=%0#10" PRIx32 "\n", istate->r24, istate->r25, istate->r26);
[7e752b2]82
[682cfceb]83 printf("r27=%0#10" PRIx32 "\tr28=%0#10" PRIx32 "\t"
84 "r29=%0#10" PRIx32 "\n", istate->r27, istate->r28, istate->r29);
[7e752b2]85
[682cfceb]86 printf("r30=%0#10" PRIx32 "\tr31=%0#10" PRIx32 "\n",
[7e752b2]87 istate->r30, istate->r31);
88
[682cfceb]89 printf("cr =%0#10" PRIx32 "\tpc =%0#10" PRIx32 "\t"
90 "lr =%0#10" PRIx32 "\n", istate->cr, istate->pc, istate->lr);
[7e752b2]91
[682cfceb]92 printf("ctr=%0#10" PRIx32 "\txer=%0#10" PRIx32 "\t"
93 "dar=%0#10" PRIx32 "\n", istate->ctr, istate->xer, istate->dar);
[7e752b2]94
[682cfceb]95 printf("srr1=%0#10" PRIx32 "\n", istate->srr1);
[5b8016d]96}
97
[ffe276f]98/** External interrupts handler
99 *
100 */
[5954241]101static void exception_external(unsigned int n, istate_t *istate)
[c782434]102{
[ffe276f]103 uint8_t inum;
[f5e39a32]104
[ffe276f]105 while ((inum = pic_get_pending()) != 255) {
[f5e39a32]106 irq_t *irq = irq_dispatch_and_lock(inum);
107 if (irq) {
108 /*
109 * The IRQ handler was found.
110 */
[7bcfbbc]111
112 if (irq->preack) {
113 /* Acknowledge the interrupt before processing */
[c2417bc]114 if (irq->cir)
115 irq->cir(irq->cir_arg, irq->inr);
[7bcfbbc]116 }
117
[6cd9aa6]118 irq->handler(irq);
[c2417bc]119
120 if (!irq->preack) {
121 if (irq->cir)
122 irq->cir(irq->cir_arg, irq->inr);
123 }
124
[ffe276f]125 irq_spinlock_unlock(&irq->lock, false);
[f5e39a32]126 } else {
127 /*
128 * Spurious interrupt.
129 */
130#ifdef CONFIG_DEBUG
[7e752b2]131 printf("cpu%u: spurious interrupt (inum=%" PRIu8 ")\n",
[ffe276f]132 CPU->id, inum);
[f5e39a32]133#endif
134 }
[c782434]135 }
136}
137
[5954241]138static void exception_decrementer(unsigned int n, istate_t *istate)
[91d5ad6]139{
[8965838e]140 start_decrementer();
[2425349]141 clock();
[91d5ad6]142}
[3debedec]143
[91d5ad6]144/* Initialize basic tables for exception dispatching */
145void interrupt_init(void)
146{
[b3b7e14a]147 exc_register(VECTOR_DATA_STORAGE, "data_storage", true,
148 pht_refill);
149 exc_register(VECTOR_INSTRUCTION_STORAGE, "instruction_storage", true,
150 pht_refill);
151 exc_register(VECTOR_EXTERNAL, "external", true,
152 exception_external);
153 exc_register(VECTOR_DECREMENTER, "timer", true,
154 exception_decrementer);
[91d5ad6]155}
[953b0f33]156
[10e0cee]157/** @}
[b45c443]158 */
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