| 1 | #
|
|---|
| 2 | # Copyright (c) 2006 Martin Decky
|
|---|
| 3 | # All rights reserved.
|
|---|
| 4 | #
|
|---|
| 5 | # Redistribution and use in source and binary forms, with or without
|
|---|
| 6 | # modification, are permitted provided that the following conditions
|
|---|
| 7 | # are met:
|
|---|
| 8 | #
|
|---|
| 9 | # - Redistributions of source code must retain the above copyright
|
|---|
| 10 | # notice, this list of conditions and the following disclaimer.
|
|---|
| 11 | # - Redistributions in binary form must reproduce the above copyright
|
|---|
| 12 | # notice, this list of conditions and the following disclaimer in the
|
|---|
| 13 | # documentation and/or other materials provided with the distribution.
|
|---|
| 14 | # - The name of the author may not be used to endorse or promote products
|
|---|
| 15 | # derived from this software without specific prior written permission.
|
|---|
| 16 | #
|
|---|
| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
|---|
| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
|---|
| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|---|
| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|---|
| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|---|
| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|---|
| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|---|
| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|---|
| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
|---|
| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|---|
| 27 | #
|
|---|
| 28 |
|
|---|
| 29 | #include <arch/asm/regname.h>
|
|---|
| 30 | #include <arch/context_offset.h>
|
|---|
| 31 | #include <arch/msr.h>
|
|---|
| 32 |
|
|---|
| 33 | .text
|
|---|
| 34 |
|
|---|
| 35 | .global fpu_context_save
|
|---|
| 36 | .global fpu_context_restore
|
|---|
| 37 | .global fpu_init
|
|---|
| 38 | .global fpu_enable
|
|---|
| 39 | .global fpu_disable
|
|---|
| 40 |
|
|---|
| 41 | .macro FPU_CONTEXT_STORE r
|
|---|
| 42 | stfd fr0, OFFSET_FR0(\r)
|
|---|
| 43 | stfd fr1, OFFSET_FR1(\r)
|
|---|
| 44 | stfd fr2, OFFSET_FR2(\r)
|
|---|
| 45 | stfd fr3, OFFSET_FR3(\r)
|
|---|
| 46 | stfd fr4, OFFSET_FR4(\r)
|
|---|
| 47 | stfd fr5, OFFSET_FR5(\r)
|
|---|
| 48 | stfd fr6, OFFSET_FR6(\r)
|
|---|
| 49 | stfd fr7, OFFSET_FR7(\r)
|
|---|
| 50 | stfd fr8, OFFSET_FR8(\r)
|
|---|
| 51 | stfd fr9, OFFSET_FR9(\r)
|
|---|
| 52 | stfd fr10, OFFSET_FR10(\r)
|
|---|
| 53 | stfd fr11, OFFSET_FR11(\r)
|
|---|
| 54 | stfd fr12, OFFSET_FR12(\r)
|
|---|
| 55 | stfd fr13, OFFSET_FR13(\r)
|
|---|
| 56 | stfd fr14, OFFSET_FR14(\r)
|
|---|
| 57 | stfd fr15, OFFSET_FR15(\r)
|
|---|
| 58 | stfd fr16, OFFSET_FR16(\r)
|
|---|
| 59 | stfd fr17, OFFSET_FR17(\r)
|
|---|
| 60 | stfd fr18, OFFSET_FR18(\r)
|
|---|
| 61 | stfd fr19, OFFSET_FR19(\r)
|
|---|
| 62 | stfd fr20, OFFSET_FR20(\r)
|
|---|
| 63 | stfd fr21, OFFSET_FR21(\r)
|
|---|
| 64 | stfd fr22, OFFSET_FR22(\r)
|
|---|
| 65 | stfd fr23, OFFSET_FR23(\r)
|
|---|
| 66 | stfd fr24, OFFSET_FR24(\r)
|
|---|
| 67 | stfd fr25, OFFSET_FR25(\r)
|
|---|
| 68 | stfd fr26, OFFSET_FR26(\r)
|
|---|
| 69 | stfd fr27, OFFSET_FR27(\r)
|
|---|
| 70 | stfd fr28, OFFSET_FR28(\r)
|
|---|
| 71 | stfd fr29, OFFSET_FR29(\r)
|
|---|
| 72 | stfd fr30, OFFSET_FR30(\r)
|
|---|
| 73 | stfd fr31, OFFSET_FR31(\r)
|
|---|
| 74 | .endm
|
|---|
| 75 |
|
|---|
| 76 | .macro FPU_CONTEXT_LOAD r
|
|---|
| 77 | lfd fr0, OFFSET_FR0(\r)
|
|---|
| 78 | lfd fr1, OFFSET_FR1(\r)
|
|---|
| 79 | lfd fr2, OFFSET_FR2(\r)
|
|---|
| 80 | lfd fr3, OFFSET_FR3(\r)
|
|---|
| 81 | lfd fr4, OFFSET_FR4(\r)
|
|---|
| 82 | lfd fr5, OFFSET_FR5(\r)
|
|---|
| 83 | lfd fr6, OFFSET_FR6(\r)
|
|---|
| 84 | lfd fr7, OFFSET_FR7(\r)
|
|---|
| 85 | lfd fr8, OFFSET_FR8(\r)
|
|---|
| 86 | lfd fr9, OFFSET_FR9(\r)
|
|---|
| 87 | lfd fr10, OFFSET_FR10(\r)
|
|---|
| 88 | lfd fr11, OFFSET_FR11(\r)
|
|---|
| 89 | lfd fr12, OFFSET_FR12(\r)
|
|---|
| 90 | lfd fr13, OFFSET_FR13(\r)
|
|---|
| 91 | lfd fr14, OFFSET_FR14(\r)
|
|---|
| 92 | lfd fr15, OFFSET_FR15(\r)
|
|---|
| 93 | lfd fr16, OFFSET_FR16(\r)
|
|---|
| 94 | lfd fr17, OFFSET_FR17(\r)
|
|---|
| 95 | lfd fr18, OFFSET_FR18(\r)
|
|---|
| 96 | lfd fr19, OFFSET_FR19(\r)
|
|---|
| 97 | lfd fr20, OFFSET_FR20(\r)
|
|---|
| 98 | lfd fr21, OFFSET_FR21(\r)
|
|---|
| 99 | lfd fr22, OFFSET_FR22(\r)
|
|---|
| 100 | lfd fr23, OFFSET_FR23(\r)
|
|---|
| 101 | lfd fr24, OFFSET_FR24(\r)
|
|---|
| 102 | lfd fr25, OFFSET_FR25(\r)
|
|---|
| 103 | lfd fr26, OFFSET_FR26(\r)
|
|---|
| 104 | lfd fr27, OFFSET_FR27(\r)
|
|---|
| 105 | lfd fr28, OFFSET_FR28(\r)
|
|---|
| 106 | lfd fr29, OFFSET_FR29(\r)
|
|---|
| 107 | lfd fr30, OFFSET_FR30(\r)
|
|---|
| 108 | lfd fr31, OFFSET_FR31(\r)
|
|---|
| 109 | .endm
|
|---|
| 110 |
|
|---|
| 111 | fpu_context_save:
|
|---|
| 112 | FPU_CONTEXT_STORE r3
|
|---|
| 113 |
|
|---|
| 114 | mffs fr0
|
|---|
| 115 | stfd fr0, OFFSET_FPSCR(r3)
|
|---|
| 116 |
|
|---|
| 117 | blr
|
|---|
| 118 |
|
|---|
| 119 | fpu_context_restore:
|
|---|
| 120 | lfd fr0, OFFSET_FPSCR(r3)
|
|---|
| 121 | mtfsf 7, fr0
|
|---|
| 122 |
|
|---|
| 123 | FPU_CONTEXT_LOAD r3
|
|---|
| 124 |
|
|---|
| 125 | blr
|
|---|
| 126 |
|
|---|
| 127 | fpu_init:
|
|---|
| 128 | mfmsr r0
|
|---|
| 129 | ori r0, r0, MSR_FP
|
|---|
| 130 |
|
|---|
| 131 | # Disable FPU exceptions
|
|---|
| 132 | li r3, MSR_FE0 | MSR_FE1
|
|---|
| 133 | andc r0, r0, r3
|
|---|
| 134 |
|
|---|
| 135 | mtmsr r0
|
|---|
| 136 | blr
|
|---|
| 137 |
|
|---|
| 138 | fpu_enable:
|
|---|
| 139 | mfmsr r0
|
|---|
| 140 | ori r0, r0, MSR_FP
|
|---|
| 141 | mtmsr r0
|
|---|
| 142 | blr
|
|---|
| 143 |
|
|---|
| 144 | fpu_disable:
|
|---|
| 145 | mfmsr r0
|
|---|
| 146 | li r3, MSR_FP
|
|---|
| 147 | andc r0, r0, r3
|
|---|
| 148 | mtmsr r0
|
|---|
| 149 | blr
|
|---|
| 150 |
|
|---|
